CTNF 19/056,671 CTNF 77727 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 2, 3 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For claim 2, the recitation “a duty ratio” on line 2 is indefinite because it is unclear antecedent basis since it is not clear if it refers to “duty ratio” recited earlier in claim 1 (see lines 6 and 7). Clarification and/or appropriate correction is required. Claim 3 is indefinite because it depends on claim 2. For claim 5, the recitation “a duty ratio” on line 10 is indefinite because it is unclear antecedent basis since it is not clear if it refers to “a duty ratio” recited earlier (see line 5). Clarification and/or appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Sugimoto (US 2007/0296474) . For claims 1 and 4, Figures 1-2 of Sugimoto teaches a control device, comprising: a processor (21, Figure 1) configured to have an output terminal for outputting a clock signal (CP0) and to execute data communication with an integrated circuit (23, Figure 1); and a signal output circuit (22 in Figure 1 which is shown in detail in Figure 2) configured to output a reset signal (RST1 outputs the reset RST signal) used for resetting the integrated circuit (23, Figure 1) in response to an input of the clock signal (CP0) having a predetermined first value (High) of duty ratio after input of the clock signal (CP0) to the integrated circuit (see [0038]-[0041], when clock CP0 is High, transmission gate TG1 is ON, so reset signal RST is passed to output RST1), and to stop output of the reset signal (reset signal RST stops output to RST1) in response to switching of the duty ratio of the clock signal (CP0) from the first value (High) to a second value (Low) lower than the first value (High) (see [0038]-[0041], when clock CP0 is Low, transmission gate TG1 is off, so reset signal RST is not passed to output RST1). For claim 4, Figure 1 is an electronic device comprising the control device of claim 1 and the integrated circuit (23). For claim 2, Figures 1-2 of Sugimoto teaches wherein the processor (21) outputs the clock signal (CP0) having a duty ratio of the first value (High) from the output terminal when the data communication is executed, and switches the duty ratio of the clock signal (CP0) output from the output terminal from the first value (High) to the second value (Low) after the data communication ends (see [0038]-[0041]). For claim 3, Figures 1-2 of Sugimoto teaches wherein the processor (21) stops output of the clock signal (CP0) from the output terminal (output CP0) after the data communication ends and after output of the reset signal (RST1 from receiving reset RST) from the signal output circuit (output RST1 of 22) stops (see [0038]-[0041]). For method claim 5, the operations of Figures 1-2 of Sugimoto teaches (as discussed above in the apparatus claims 1-4 above) teaches all the method steps of this claim, i.e., Figures 1-2 of Sugimoto teaches a control device, comprising: a processor (21, Figure 1) configured to have an output terminal that outputs a clock signal (CP0), and to execute data communication with an integrated circuit (23); and a signal output circuit (22 in Figure 1 which is shown in detail in Figure 2) configured to output a reset signal (RST1 outputs the reset RST signal) used for resetting the integrated circuit (23) in response to an input of the clock signal (CP0) having a duty ratio of a predetermined first value (High) after the input of the clock signal (CP0) to the integrated circuit (see [0038]-[0041], when clock CP0 is High, transmission gate TG1 is ON, so reset signal RST is passed to output RST1) and to stop output of the reset signal (reset signal RST stops output to RST1) in response to switching of the duty ratio of the clock signal (CP0) from the first value (High) to a second value lower (Low) than the first value (High), (see [0038]-[0041], when clock CP0 is Low, transmission gate TG1 is off, so reset signal RST is not passed to output RST1); the control method comprising: an output step of outputting the clock signal (CP0) having a duty ratio of the first value (High) from the output terminal (output of 21) when the data communication is executed; and a switching step of switching the duty ratio of the clock signal (CP0) output from the output terminal (output of 21) from the first value (High) to the second value (Low) after the data communication ends (see [0038]-[0041]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Duley (USP 5,561,389) in Figure 6 teaches a clock conditioning circuit for microprocessor application. Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2842 Application/Control Number: 19/056,671 Page 2 Art Unit: 2842 Application/Control Number: 19/056,671 Page 3 Art Unit: 2842 Application/Control Number: 19/056,671 Page 4 Art Unit: 2842 Application/Control Number: 19/056,671 Page 5 Art Unit: 2842
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