DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Thien (US 20190130815) in view of Murata (US 20100005327).
As to claim 1, Thien discloses a memory system comprising:
at least one memory device (fig. 5, memory 526); and
a controller (processor 524) configured to perform data communication with at least one external device (device 102) via a computer-memory link-based interface and transfer (cable 136), to the at least one memory device (memory 526), an input/output request received from the at least one external device (par 18 “receiving a request”); and
wherein the controller is configured to:
check a first interface version (par. 28) of a first external device among the at least one external device (fig. 4 s402, check to select a version of a set of parameter values);
apply a setting value for changing a controller register configuration according to the first interface version (“apply a set of parameter values”);
processing a request received from the first external device (s406, initiate link training).
Thien does not disclose the step of writing, into a firmware binary, a setting value for changing a controller register configuration according to the first interface version. In the same field of art (peripheral configuration), Murata discloses a method of operating a storage device capable of being compatible with various hosts and capable of performing power throttling (par. 5). In one embodiment, Murata further discloses a memory system comprising: at least one memory device (memory 12) and a controller (controller 13) configured to perform data communication with at least one external device (device 19) via a computer-memory link-based interface and transfer (par. 28), to the at least one memory device (“data is transferred between the USB device 19 and the CPU 11”), wherein the controller is configured to: check a first interface version of a first external device among the at least one external device (par 44, “determines the type of the connected device 19”); and write, into a firmware binary, a setting value for changing a controller register configuration according to the first interface version (“changes the values of the registers”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murata and Thien, by writing, into a firmware binary, a setting value for changing a controller register configuration according to the first interface version. The motivation is to improve the power consumption and the performance of the system (par. 10).
As to claim 6, Thien/Murata discloses the memory system according to claim 1, wherein the controller, operatively engaged with a memory (Murata, fig. 2 memory 24) including an extended area available for a register configuration (r1, r2, r3) is configured to set , as a default value (par. 44 “[1, 0, 0]”), the controller register configuration (“[1,1,0]”) corresponding to the first interface version of the first external device (“USB 1.1 type”), when the first interface version of the first external device is older than a version (“USB 2.0 type”) corresponding to the predetermined controller register configuration (“[1,0,1]”).
As to claim 7, Thien/Murata discloses the memory system according to claim 1,
wherein the at least one external device further comprises a second external device (Murata, fig. 4. Note: The system is configured to connect with devices) having a second interface version (s14 USB 2.0 device) different from the first interface version of the first external device (s9 USB 1.1), and
wherein the controller is configured to:
write, into the firmware binary, a setting value for changing the controller register configuration according to the second interface version of the second external device (par. 44); and
process a request by referring to at least one of values stored in the firmware binary depending on whether the request is received from either the first external device or the second external device (Thien, fig. 4).
As to claim 8, Thien/Murata discloses the memory system according to claim 7, wherein the controller is configured to add a first controller register configuration corresponding to a recent interface version among the first and second interface versions of the first and second external devices (par. 44), into an extended area storing a second controller register configuration (“[1,1,0]”) corresponding to an older interface version (“USB 1.1”) among the first and second interface versions of the first and second external devices.
As to claim 10, all the same elements of claim 1 are listed, but in a method form with at least on host (CPU 11 and at least one memory device (memory 12). Therefore, the supporting rationale of the rejection to claim 1 applies equally to claim 10.
Claims 2-5, 11-13, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Thien in view of Murata and further in view of Das Sharma et al (US 20220327083, Sharma).
As to claim 2, Thien/Murata discloses the memory system according to claim 1, but does not disclose the limitations in claim 2. In the same field of art (peripheral configuration), Sharma discloses a controller (fig. 12 adapter die 1) is further configured to perform a Link Training and Status State Machine (LTSSM) operation (fig. 8) for configurating controller registers (“lp_state_req = Active”) in response to an active state request received from a first external device (par. 91 “request for the RDI to move into an active state”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien/Murata and Sharma, by configuring the controller further to perform a Link Training and Status State Machine (LTSSM) operation for configurating controller registers in response to an active state request received from the first external device. The motivation is to improve the performance of the system (par. 2).
As to claim 3, Thien/Murata/Sharma discloses the memory system according to claim 2, wherein the controller is configured to:
check the first interface version of the first external device during the LTSSM operation (Murata, par. 44);
determine whether the first interface version of the first external device and the controller register configuration are compatible (fig. 6 S2, S55); and
perform data object exchange (DOE) with the first external device based on the setting value according to a compatibility to store a result of the DOE in the firmware binary (Sharma, fig. 12 “training parameter exchanges 1230”).
As to claim 4, Thien/Murata/Sharma discloses the memory system according to claim 2, wherein the controller is configured to transmit, to the at least one external device, the setting value set before the LTSSM operation is performed, when the at least one external device transmits a read request for the controller register configuration during the LTSSM operation (Sharma, par. 41).
As to claim 5, Thien/Murata discloses the memory system according to claim 1, but does not disclose the limitations in claim 5. In the same field of art (peripheral configuration), Sharma discloses a controller is configured to perform a LTSSM operation for performing the data communication (fig. 8), when a link request according to an Active Link Management Protocol (ALMP) handshake is received from the at least one external device (fig. 13, par. 103, 104). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien/Murata and Sharma, by configuring the controller to perform a LTSSM operation for performing the data communication, when a link request according to an Active Link Management Protocol (ALMP) handshake is received from the at least one external device. The motivation is to improve the performance of the system (par. 2).
As to claim 11, Thien/Murata discloses the computer-memory link-based apparatus according to claim 10, wherein a LTSSM operation comprises:
a first operation for determining a data communication speed with the first host (par. 20 “maximum link rate”); and
a second operation for determining the controller register configuration (“differential or a single ended” and other parameters).
Thien does not disclose wherein the controller is configured to perform a Link Training and Status State Machine (LTSSM) operation for the controller register configuration in response to an active state request received from the first external device. In the same field of art (peripheral configuration), Sharma discloses a controller (fig. 12 adapter die 1) is further configured to perform a Link Training and Status State Machine (LTSSM) operation (fig. 8) for configurating controller registers (“lp_state_req = Active”) in response to an active state request received from a first external device (par. 91 “request for the RDI to move into an active state”) wherein the LTSSM operation comprises: a first operation for determining a data communication speed with the first host (par. 62); and a second operation for determining the controller register configuration (par. 75). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien/Murata and Sharma, by configuring the controller further to perform a Link Training and Status State Machine (LTSSM) operation for configurating controller registers in response to an active state request received from the first external device. The motivation is to improve the performance of the system (par. 2).
As to claims 12-13, all the same elements of claims 3-4 are listed, but in a method form. Therefore, the supporting rationale of the rejection to claims 3-4 applies equally to claims 12-13.
As to claim 15, Thien discloses a method for operating a system, the method comprising: performing a configuration based on a firmware binary (fig. 4 s402) after power is supplied (par. 23);
performing a Link Training and Status State Machine (LTSSM) operation (s406);
checking (s408) an interface version of an external device (device 102);
determining whether the interface version of the external device and the configuration are compatible (s410. Note: Link scores represent a level of compatibility);
updating the setting value and storing an updated setting value in the firmware binary (s418).
Thien does not disclose the register configuration. In the same field of art (peripheral configuration), Murata discloses a method of operating a storage device capable of being compatible with various hosts and capable of performing power throttling (par. 5). In one embodiment, Murata further discloses a memory system comprising: at least one memory device (memory 12) and a controller (controller 13) configured to perform data communication with at least one external device (device 19) via a computer-memory link-based interface and transfer (par. 28), to the at least one memory device (“data is transferred between the USB device 19 and the CPU 11”), wherein the controller is configured to: check a first interface version of a first external device among the at least one external device (par 44, “determines the type of the connected device 19”); and write, into a firmware binary, a setting value for changing a controller register configuration according to the first interface version (“changes the values of the registers”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Murata and Thien, by performing a configuration based on a firmware binary (fig. 4 s402) after power is supplied. The motivation is to improve the power consumption and the performance of the system (par. 10).
Thien does not disclose an active state request and the step of performing a DOE exchange as claimed. In the same field of art (peripheral configuration), Sharma discloses the step of performing a Link Training and Status State Machine (LTSSM) operation (fig. 8) for configurating controller registers (fig. 12, “lp_state_req = Active”) in response to an active state request received from a first external device (par. 91 “request for the RDI to move into an active state”) and performing a Data Object Exchange (DOE) with the external device (fig. 12, “SB exchange”, fig. 13 “protocol parameter exchange”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien and Sharma, by performing a Link Training and Status State Machine (LTSSM) operation (s406) in response to an active state request received from an external device and performing a Data Object Exchange (DOE) with the external device for a setting value based on a compatibility. The motivation is to improve the performance of the system (par. 2).
As to claims 16-19, all the same elements of claims 4-6 are listed but in a method form. Therefore, the supporting rationale of the rejection to claims 4-6 applies equally to claims 16-19.
Claims 9, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Thien a in view of Murata and further in view of Athanikar et al (US 20240020000, Athanikar).
As to claim 9, Thien/Murata discloses the memory system according to claim 1, but does not disclose the limitations in claim 9. In the same field of art (peripheral configuration), Athanikar discloses a controller is configured to store the firmware binary (firmware 111, register 110) in a non-volatile memory (flash memory 109) operatively engaged with the controller (par. 30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien/Murata and Athanikar, by configuring the controller is to store the firmware binary in a non-volatile memory operatively engaged with the controller. The motivation is to improve the reliability of the system (par. 21).
As to claim 14, all the same elements of claim 9 are listed but in a method form. Therefore, the supporting rationale of the rejection to claim 9 applies equally to claim 14.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Thien a in view of Murata/Sharma and further in view of Athanikar.
As to claim 20, Thien/Murata/Sharma the method according to claim 19, but does not disclose the limitations in claim 20. In the same field of art (peripheral configuration), Athanikar discloses a controller is configured to store the firmware binary (firmware 111, register 110) in a non-volatile memory (flash memory 109) operatively engaged with the controller (par. 30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thien/Murata/Sharma and Athanikar, by further comprising storing the firmware binary in a non-volatile memory. The motivation is to improve the reliability of the system (par. 21).
Conclusion
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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