DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 19, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the second threshold voltage distribution" in line 9. There is insufficient antecedent basis for this limitation in the claim. The claim recites a “second threshold voltage” in lines 3-4. For purposes of examination, these items have both been interpreted to refer to a second threshold voltage distribution.
Claims 3-7 depend from claim 2, and so are seen to contain the same deficiencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Cai et al (U.S. Patent Pub. No. 2017/0132125), hereinafter referred to as Cai, in view of Singidi et al (U.S. Patent Pub. No. 2019/0130983), hereinafter referred to as Singidi.
In regard to claim 1, Cai teaches a memory system, comprising: a memory device including a plurality of blocks (Fig. 2 flash memory 210 having blocks); and a memory controller (Fig. 2 memory controller 250) configured to: determine a page type in which a data migration operation is to be performed based on a degradation type of a first block that is read among the plurality of blocks (¶ 0067, different page types in a block have different error characteristics; ¶ 0068 LSB pages can tolerate greater read disturb and so are reclaimed less frequently from blocks; therefore to a person of ordinary skill, page type selection is functionally based on degradation type), and control the memory device to perform the data migration operation of migrating data of target pages to pages in a second block, the target pages determined based on the page type among multiple pages included in the first block (¶ 0067 blocks are separated into sub-blocks for different page types and reclaimed based on differing error rates; ¶ 0076 only selected page types are moved to new blocks when reclaimed).
Cai does not teach the remaining limitations of claim 1. However, Singidi teaches an embodiment including determining a target based on an operating state of the memory device (¶ 0075, lines 11-15 read counter comparison may be performed during idle periods; ¶ 0077, lines 7-13 "remedial action" (i.e. wear leveling) may be performed at the end of the comparison operation). If combined with the process of Cai, migration and page selection would only be performed based on the controller being idle (e.g. idle operating state), achieving the claimed limitation of determin[ing] a page type in which a data migration operation is to be performed based on an operating state of the memory device and a degradation type of a first block. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Singidi in order to prevent wear leveling while a device is busy and benefit from techniques for memory access and control which may compensate for memory device performance changes according to wear (¶ 0099, lines 4-7).
Claims 2-5, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Singidi, Li et al (Taiwan Patent No. I805183), hereinafter referred to as Li, and Park (U.S. Patent Pub. No. 2017/0168891).
As for claim 2, the previously cited references teach the memory system of claim 1. They do not teach the remaining limitations of claim 2. However, Park teaches an embodiment wherein the memory controller is configured to determine the degradation type of the first block based on at least one of a first threshold voltage distribution or a second threshold voltage distribution (¶ 0085 a first (erase level) reference threshold voltage is used to determine read disturb when compared to the voltage distributions), wherein the second threshold voltage distribution corresponds to a highest program state in which the threshold voltage is highest (¶ 0086 a second (highest level) reference voltage and distribution is used to determine charge loss (retention)). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Park in order to determine block error types and improve reliability and performance (¶ 0031).
The previously cited references do not explicitly teach the remaining limitations of claim 2. However, Li teaches performing read voltage adjustment (e.g. wear leveling) in response to a determination that the operating state of the memory device is a busy state and an error correction operation on data read from the first block fails (Page 21, ¶ 3, lines 3-5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Li in order to recover from ECC failures and improve read performance of a memory system (Page 8, ¶ 3, lines 1-3).
As for claim 3, the previously cited references teach the system of claim 2. They do not teach the remaining limitations of claim 3. However, Park teaches a memory controller (¶ 0059 error detection and handling is done by memory controller) configured to determine the degradation type of the first block as a read disturb type in response to a determination that the first threshold voltage distribution is greater than a first reference threshold voltage distribution corresponding to the lowest program state (¶ 0085 a first (erase level) reference threshold voltage is used to count a number of cells enabled by the voltage (cells having a threshold voltage below the reference), and a decrease compared to the initial reference indicates read disturbance; ¶ 0087 system may perform this determination) and determine the degradation type of the first block as a retention type in response to a determination that the first threshold voltage distribution is less than the first reference threshold voltage distribution and the second threshold voltage distribution is less than a second reference threshold voltage distribution corresponding to the highest program state (¶ 0086 a second (highest level) reference voltage is used to count a number of cells enabled, and an increase compared to the initial reference indicates charge loss (retention) error; ¶ 0088 cell counts may use both reference voltages).
As for claim 4, Applicant is directed to the rejection of claim 3, as the limitation has been addressed in the rationale. (Park ¶ 0085 a first (erase level) reference threshold voltage is used to count a number of cells enabled by the voltage (on-cells), and a decrease compared to the initial reference count indicates read disturbance; ¶ 0087 system may perform this determination).
As for claim 5, Applicant is directed to the rejection of claim 3, as the main limitation has been addressed in the rationale. Additionally, in the embodiment of Park's disclosure wherein both reference voltages are used for cell counts (¶ 0088), the cell-count operation would functionally determine that the number of on-cells at each reference voltage is greater than the reference count when charge loss is detected, achieving the claimed limitation.
As for claim 19, Applicant is directed to the rejection of claim 2, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 22, Applicant is directed to the rejection of claim 3, as the claims are directed to the same limitations and therefore rejected on the same rationale.
Claims 6, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Singidi, Li, Park, and Tao et al (U.S. Patent Pub. No. 2020/0097189), hereinafter referred to as Tao.
As for claim 6, the previously cited references teach the system of claim 3. They do not explicitly teach the remaining limitations of claim 6. However, Tao discloses a memory device which may determine a first calibration read voltage corresponding to a first read voltage based on a result of the error correction operation (¶ 0026, lines 1-8 encode/decode engine includes ECC decoder; ¶ 0035 a shifted voltage is used if decoder fails to read data), and to determine the degradation type of the first block as the read disturb type in response to a determination that the first calibration read voltage is greater than the first read voltage (¶ 0039, lines 1-7 shifted voltage is determined to be greater or less than first voltage; ¶ 0043 this decides data retention recovery or disturb recovery). Tao does not explicitly disclose this process for the lowest program state, however it would inevitably occur during operation of the disclosed device in combination (for ex. when reading a cell at level E in Park's disclosure), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Tao in order to dynamically identify read errors and more efficiently store data to improve storage system performance (¶ 0027, lines 1-5).
As for claim 17, Applicant is directed to the rejection of claim 6, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 20, the previously cited references teach the memory controller of claim 17. Additionally, Cai discloses determine the page type based on a page group having a largest number of fail bits (¶ 0067 lines 1-4 pages with the worst error rate (e.g. more fail bits) are prioritized) among a first page group, a second page group, and a third page group included in the first block , wherein most significant bit (MSB) data is stored in the first page group, central significant bit (CSB) data is stored in the second page group, and least significant bit (LSB) data is stored in the third page group (¶ 0072 device blocks may include MSB, CSB, and LSB pages).
Claims 12-14, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Singidi, Song et al (U.S. Patent Pub. No. 2022/0350535), hereinafter referred to as Song, and Sun (U.S. Patent Pub. No. 2011/0022744).
As for claim 12, the previously cited references teach the system of claim 1. They do not explicitly teach the remaining limitations of claim 12. However, Song teaches detecting a busy or idle state based on a number of commands in a command queue (¶ 0082 issued command buffer is a form of command queue; can be used to determine if idle or busy; Fig. 3 controller 315 includes power mode controller 330). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Song in order to determine power states and conserve power (¶ 0012, lines 1-2). Song does not teach detecting an idle or busy state based on a power supply time, however Sun discloses that this is a common technique in prior art (¶ 0007, lines 1-5 disclose that a storage controller will commonly start in a busy state for a certain amount of time when a device is connected (e.g. powered on)). This specific limitation applies this known technique to achieve the expected effect of preventing transmission of commands before a storage device is ready (¶ 0007, lines 8-11), preventing potential command failures.
As for claim 13, the previously cited references teach the system of claim 12. Additionally, the prior art disclosure of Sun outlined in the rejection of claim 12 would result in a memory controller determining a memory device as being in the busy state if power-on time is under 30 seconds (¶ 0007, lines 1-5), achieving the claimed limitation.
As for claim 14, the previously cited references teach the system of claim 12. Additionally, Song teaches that a device is only considered eligible for a low-power mode transition if the quantity of queued commands is less than a threshold or 0 (¶ 0086, lines 1-9 disclose transitioning for a "break in access" i.e. idle state), therefore the controller may also detect that the device is busy based on a number of commands being above a threshold, achieving the claimed limitation.
As for claim 18, Applicant is directed to the rejection of claim 12, as the claims are directed to the same limitations and therefore rejected on the same rationale.
As for claim 21, Applicant is directed to the rejection of claim 12, as the claims are directed to the same limitations and therefore rejected on the same rationale.
Allowable Subject Matter
Claims 7-11, 15-16, and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 includes the limitations of the memory system according to claim 6, wherein the memory controller is configured to determine a second calibration read voltage corresponding to a second read voltage for the highest program state based on the result of the error correction operation, and to determine the degradation type of the first block as the retention type in response to a determination that the first calibration read voltage is less than the first read voltage and the second calibration read voltage is less than the second read voltage. No reference was found to teach, alone or in combination, the entirety of the claimed limitations. Specifically, the limitation of determin[ing] the degradation type of the first block as the retention type in response to a determination that the first calibration read voltage is less than the first read voltage and the second calibration read voltage is less than the second read voltage was not found to be sufficiently taught by prior art. Reference Tao discloses determination of a retention error based on a single calibration voltage, but not two distinct voltages at separate levels.
Claim 8 includes the limitations of the memory system according to claim 1, wherein: the first block includes a first page group in which most significant bit (MSB) data is stored, a second page group in which central significant bit (CSB) data is stored, and a third page group in which least significant bit (LSB) data is stored, the memory device counts a number of fail bits in each of the first page group, the second page group, and the third page group, and the memory controller determines the degradation type of the first block as the read disturb type in response to a determination that the operating state of the memory device is a busy state and the first page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits, and determines the target pages as pages included in the first page group in response to a determination that the degradation type of the first block is the read disturb type. No reference was found to teach, alone or in combination, the entirety of the claimed limitations. Specifically, the limitation of determin[ing] the degradation type of the first block as the read disturb type in response to a determination that the operating state of the memory device is a busy state and the first page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits was not found to be sufficiently taught by prior art.
Claims 9-11 would be found allowable by virtue of dependence on allowable claim 8.
Claim 15 includes the limitations of the memory system according to claim 12, wherein the memory controller is configured to determine a part of the pages included in the first block as the target pages in response to a determination that the operating state of the memory device is determined to be the busy state. No reference was found to teach, alone or in combination, the entirety of the claimed limitations. Reference Gorobets (U.S. Patent Pub. No. 2008/0294814) was found to teach reclamation operations being dynamically performed based on busy/idle status, but does not disclose selecting only certain pages based on a busy state.
Claim 16 would be found allowable by virtue of dependence on allowable claim 15.
Claim 23 includes the limitations of the method according to claim 21, wherein determining the degradation type of the first block comprises: counting a number of fail bits in each of a first page group, a second page group, and a third page group included in the first block, wherein most significant bit (MSB) data is stored in the first page group, central significant bit (CSB) data is stored in the second page group, and least significant bit (LSB) data is stored in the third page group; determining the degradation type of the first block as a read disturb type in response to a determination that the first page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits; determining the degradation type of the first block as a first retention type in response to a determination that the second page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits; and determining the degradation type of the first block as a second retention type in response to a determination that the third page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits. No reference was found to teach, alone or in combination, the entirety of the claimed limitations. Specifically, the limitation of and determining the degradation type of the first block as a second retention type in response to a determination that the third page group, among the first page group, the second page group, and the third page group, has a largest number of fail bits was not found to be sufficiently taught by prior art. Reference Kim et al (U.S. Patent Pub. No. 2022/0005535) discloses detecting read disturb and data retention errors based on page bit errors, but does not specify a third page group or second retention type error.
Claim 24 includes the same limitations as claim 8, and would therefore additionally be found allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim discloses techniques related to identifying error types based on page types.
Selected pages of “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives” disclose techniques for error detection and mitigation similar to those of the instant application and cited references.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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