DETAILED ACTION
The instant application having Application No. 19/057,055 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/057,055 filed 2/19/2025 is a Continuation of 17/703,759, filed 3/24/2022, now U.S. Patent #12265725.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/19/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where claims 1, 12, and 20 recite ‘the LTU identifier’, there is insufficient antecedent basis for this term in the claims.
Claims 2-11 and 13-19 are rejected for being dependent on a rejected claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12265725. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19057055
U.S. Patent # 12265725 (corresponding to Application # 17703759)
1. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, using the metadata, a memory access operation specified by the memory access request.
2. The system of claim 1, wherein the processing device comprises a hardware accelerator to perform the operations except for the identifying.
3. The system of claim 2, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and a system tag data structure, wherein the operations further comprise:
storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and
retrieving, by the hardware accelerator, the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure.
1. A system comprising:
a non-volatile memory device;
a volatile memory device configured to store a mapping data structure that maps a zone of a plurality of zones of logical block address (LBA) space to a physical address space of the non-volatile memory device, wherein the zone comprises a plurality of LBAs that are sequentially mapped to a plurality of physical addresses of the physical address space;
a processing device coupled to the non-volatile memory device and the volatile memory device, the processing device to perform operations comprising: creating a logical transfer unit (LTU) corresponding to an LBA received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of the zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA; and
a hardware accelerator coupled the volatile memory, the hardware accelerator to perform operations comprising:
retrieving, from the volatile memory device, an LTU identifier associated with the LTU;
determining a zone identifier (ID) based on the LTU identifier;
retrieving, from the mapping data structure, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space that includes the plurality of physical addresses; and
storing, to the volatile memory device, the metadata for use used in determining and utilizing the physical address to perform a read operation specified by the read request.
2. The system of claim 1, wherein:
the volatile memory device is configured to further store a system tag data structure;
the operations performed by the processing device further comprise storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and
the operations performed by the hardware accelerator further comprise retrieving the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure.
4. The system of claim 3, wherein the hardware accelerator comprises one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure;
a location of the mapping data structure in the volatile memory device; or
an ID mask in an entry that is set to invalid.
10. The system of claim 1, wherein the hardware accelerator comprises one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure;
a location of the mapping data structure in the volatile memory device; or
an ID mask in an entry that is set to invalid.
5. The system of claim 3, wherein operations performed by the hardware accelerator further comprise:
storing the metadata in the system tag data structure in association with the system tag; and
sending a system tag identifier for the system tag to a command generation processor of the processing device, and wherein the command generation processor of the processing device is further to generate a read command using the metadata stored with the system tag in the system tag data structure.
4. The system of claim 2, wherein operations performed by the hardware accelerator further comprise:
storing the metadata in the system tag data structure in association with the system tag; and
sending a system tag identifier for the system tag to a command generation processor of the processing device, and wherein the command generation processor of the processing device is further to generate a read command using the metadata stored with the system tag in the system tag data structure.
6. The system of claim 2, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a page map entry identifier, wherein the hardware accelerator is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
5. The system of claim 1, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier or hash value to a page map entry identifier, wherein the hardware accelerator is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
7. The system of claim 2, wherein, to determine the zone ID, the operations performed by the hardware accelerator further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
6. The system of claim 1, wherein, to determine the zone ID, the operations performed by the hardware accelerator further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
8. The system of claim 2, wherein operations performed by the hardware accelerator further comprise:
calculating a hash value of the zone ID; and
indexing into the mapping data structure using the hashed zone ID.
3. The system of claim 1, wherein operations performed by the hardware accelerator further comprise:
calculating a hash value of the zone ID; and
indexing into the mapping data structure using the hashed zone ID.
9. The system of claim 1, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the operations further comprise managing the zone map data structure.
7. The system of claim 1, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the operations performed by the hardware accelerator further comprise managing the zone map data structure.
10. The system of claim 1, wherein the mapping data structure comprises:
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the operations further comprise managing the zone-to-block set data structure; and
a block set map data structure to map the block set ID to block identifiers of physical blocks within the physical address space.
8. The system of claim 1, wherein the mapping data structure comprises:
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware accelerator is to manage the zone-to-block set data structure; and
a block set map data structure to map the block set ID to block identifiers of physical blocks within the physical address space.
11. The system of claim 1, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory device, wherein the operations further comprise managing the write sequence data structure.
9. The system of claim 1, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the non-volatile memory device, wherein the hardware accelerator is to manage the write sequence data structure.
12. A memory controller comprising:
hardware logic coupled to a memory device, the hardware logic to perform operations comprising:
identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, using the metadata, a memory access operation specified by the memory access request.
13. The memory controller of claim 12, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and a system tag data structure, wherein the operations further comprise:
storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and
retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure.
14. The memory controller of claim 13, wherein the operations further comprise:
retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure;
determining a hash value of the zone ID;
indexing, using at least one of the hash value or the LTU identifier, into the mapping data structure to retrieve the metadata; and
storing the metadata in the system tag data structure in association with the system tag.
11. A memory controller comprising:
a volatile memory configured to store a mapping data structure that maps a zone of a plurality of zones of logical block address (LBA) space to a physical address space of a non-volatile memory device, wherein the zone comprises a plurality of LBAs that are sequentially mapped to a plurality of physical addresses; and
a processing device comprising hardware logic coupled to the non-volatile memory device and the volatile memory, the hardware logic to perform operations comprising:
creating a logical transfer unit (LTU) corresponding to an LBA received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of the zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA;
retrieving, from the volatile memory, an LTU identifier associated with the LTU;
determining a zone identifier (ID) based on the LTU identifier;
retrieving, from the mapping data structure, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space that includes the plurality of physical addresses; and
storing, to the volatile memory, the metadata used in determining and utilizing the physical address to perform a read operation specified by the read request.
12. The memory controller of claim 11, wherein the volatile memory further comprises a system tag data structure configured to store a system tag comprising the LTU identifier corresponding to the LTU.
15. The memory controller of claim 12, wherein the operations further comprise:
retrieving the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure;
determining a hash value of the zone ID;
indexing, using at least one of the hash value or the LTU identifier, into the mapping data structure to retrieve the metadata; and
storing the metadata in the system tag data structure in association with the system tag.
15. The memory controller of claim 12, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a die identifier, a block identifier, and a page map entry identifier, wherein the hardware logic is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
13. The memory controller of claim 11, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a die identifier, a block identifier, and a page map entry identifier, wherein the hardware logic is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
16. The memory controller of claim 12, further comprising one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure; or
a location in memory of the mapping data structure.
14. The memory controller of claim 11, further comprising one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure; or
a location in memory of the mapping data structure.
17. The memory controller of claim 12, wherein, to determine the zone ID, the operations further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
16. The memory controller of claim 11, wherein, to determine the zone ID, the operations further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
18. The memory controller of claim 12, wherein the mapping data structure comprises:
a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware logic is to manage the zone map data structure; and
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware logic is to manage the zone-to-block set data structure.
17. The memory controller of claim 11, wherein the mapping data structure comprises:
a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware logic is to manage the zone map data structure; and
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware logic is to manage the zone-to-block set data structure.
19. The memory controller of claim 12, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory device, wherein the hardware logic is to manage the write sequence data structure.
18. The memory controller of claim 11, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the non-volatile memory device, wherein the hardware logic is to manage the write sequence data structure.
20. A method comprising:
identifying, by a processing device coupled to a memory device, a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, by the processing device, using the metadata, a memory access operation specified by the memory access request.
19. A method comprising:
creating, by a processing device of a memory sub-system that includes a non-volatile memory device, a logical transfer unit (LTU) corresponding to a logical block address (LBA) received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of LBA space of the non-volatile memory device, wherein one of the subset is the LBA, and wherein the zone of LBA space is at least a part of a logical address space of a host application mapped to a plurality of physical addresses of the non-volatile memory device;
retrieving, by a hardware accelerator of the memory sub-system from a volatile memory device, an LTU identifier associated with the LTU;
determining a zone identifier (ID) based on the LTU identifier;
retrieving, from a mapping data structure stored in volatile memory, by the hardware accelerator using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space that includes the plurality of physical addresses; and
storing, by the hardware accelerator, to the volatile memory device, the metadata used in determining and utilizing the physical address to perform a read operation specified by the read request.
The double patenting rejection above applies to claims 1-20.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 3-11, 13-16, 18-20 of U.S. Patent No. 11314446. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Instant application 19057055
U.S. Patent # 11314446 (corresponding to Application # 16912402)
1. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, using the metadata, a memory access operation specified by the memory access request.
2. The system of claim 1, wherein the processing device comprises a hardware accelerator to perform the operations except for the identifying.
3. The system of claim 2, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and a system tag data structure, wherein the operations further comprise:
storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and
retrieving, by the hardware accelerator, the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure.
1. A system comprising:
a non-volatile memory device;
a volatile memory device configured to store:
a mapping data structure that maps a zone of a logical block address (LBA) space to a physical address space of the non-volatile memory device, wherein the zone comprises a plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses; and
a system tag data structure; and
a processing device coupled to the non-volatile memory device and the volatile memory device, the processing device configured to:
create a logical transfer unit (LTU) from an LBA received in a read request, wherein the LTU comprises a subset of the plurality of sequential LBAs, wherein one of the subset is the LBA; and
store a system tag, which contains an LTU identifier for the LTU, in the system tag data structure; and
wherein the processing device comprises a hardware accelerator configured to:
retrieve the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure;
determine a zone identifier (ID) based on the LTU identifier;
index, using at least one of the zone ID or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and
store the metadata in the system tag data structure in association with the system tag.
4. The system of claim 3, wherein the hardware accelerator comprises one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure;
a location of the mapping data structure in the volatile memory device; or
an ID mask in an entry that is set to invalid.
10. The system of claim 1, wherein the hardware accelerator comprises one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure; or
a location of the mapping data structure in the volatile memory device.
5. The system of claim 3, wherein operations performed by the hardware accelerator further comprise:
storing the metadata in the system tag data structure in association with the system tag; and
sending a system tag identifier for the system tag to a command generation processor of the processing device, and wherein the command generation processor of the processing device is further to generate a read command using the metadata stored with the system tag in the system tag data structure.
4. The system of claim 1, wherein, after storing the metadata in association with the system tag, the hardware accelerator is to send a system tag identifier for the system tag to a command generation processor of the processing device, and wherein the command generation processor of the processing device is further to generate a read command using the metadata stored with the system tag in the system tag data structure.
6. The system of claim 2, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a page map entry identifier, wherein the hardware accelerator is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
5. The system of claim 1, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a page map entry identifier, wherein the hardware accelerator is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
7. The system of claim 2, wherein, to determine the zone ID, the operations performed by the hardware accelerator further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
6. The system of claim 1, wherein, to determine the zone ID, the hardware accelerator is further to:
access, within a firmware configurable register, a zone size value; and
calculate the zone ID using the LTU identifier and the zone size value.
8. The system of claim 2, wherein operations performed by the hardware accelerator further comprise:
calculating a hash value of the zone ID; and
indexing into the mapping data structure using the hashed zone ID.
3. The system of claim 1, wherein the hardware accelerator is further to calculate a hash value of the zone ID with which to perform the indexing into the mapping data structure.
9. The system of claim 1, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the operations further comprise managing the zone map data structure.
7. The system of claim 1, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware accelerator is to manage the zone map data structure.
10. The system of claim 1, wherein the mapping data structure comprises:
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the operations further comprise managing the zone-to-block set data structure; and
a block set map data structure to map the block set ID to block identifiers of physical blocks within the physical address space.
8. The system of claim 1, wherein the mapping data structure comprises:
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware accelerator is to manage the zone-to-block set data structure; and
a block set map data structure to map the block set ID to block identifiers of physical blocks within the physical address space.
11. The system of claim 1, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory device, wherein the operations further comprise managing the write sequence data structure.
9. The system of claim 1, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the non-volatile memory device, wherein the hardware accelerator is to manage the write sequence data structure.
12. A memory controller comprising:
hardware logic coupled to a memory device, the hardware logic to perform operations comprising:
identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, using the metadata, a memory access operation specified by the memory access request.
13. The memory controller of claim 12, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and a system tag data structure, wherein the operations further comprise:
storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and
retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure.
14. The memory controller of claim 13, wherein the operations further comprise:
retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure;
determining a hash value of the zone ID;
indexing, using at least one of the hash value or the LTU identifier, into the mapping data structure to retrieve the metadata; and
storing the metadata in the system tag data structure in association with the system tag.
11. A processing device comprising:
volatile memory comprising:
a system tag data structure configured to store a system tag comprising a logical transfer unit (LTU) identifier corresponding to an LTU, wherein the LTU comprises a subset of a plurality of sequential logical block addresses (LBAs),
wherein one of the subset is an LBA of a read request; and
a mapping data structure that maps a zone of an LBA space to a physical address space of a memory sub-system, wherein the zone comprises the plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses; and
hardware logic coupled to the volatile memory, the hardware logic configured to:
retrieve the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure;
determine a zone identifier (ID) based on the LTU identifier;
determine a hash value of the zone ID;
index, using at least one of the hash value or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and
store the metadata in the system tag data structure in association with the system tag.
15. The memory controller of claim 12, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a die identifier, a block identifier, and a page map entry identifier, wherein the hardware logic is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
13. The processing device of claim 11, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a die identifier, a block identifier, and a page map entry identifier, wherein the hardware logic is to manage the logical-to-physical block map data structure; and
a page map data structure indexed by the page map entry identifier to provide a page identifier.
16. The memory controller of claim 12, further comprising one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure; or
a location in memory of the mapping data structure.
19. The processing device of claim 11, further comprising one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of:
a number of bits for the LTU identifier;
an entry size for the mapping data structure; or
a location in memory of the mapping data structure in the memory sub-system.
17. The memory controller of claim 12, wherein, to determine the zone ID, the operations further comprise:
accessing, within a firmware configurable register, a zone size value; and
calculating the zone ID using the LTU identifier and the zone size value.
14. The processing device of claim 11, wherein, to determine the zone ID, the hardware logic is further to:
access, within a firmware configurable register, a zone size value; and
calculate the zone ID using the LTU identifier and the zone size value.
18. The memory controller of claim 12, wherein the mapping data structure comprises:
a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware logic is to manage the zone map data structure; and
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware logic is to manage the zone-to-block set data structure.
15. The processing device of claim 11, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware logic is to manage the zone map data structure.
16. The processing device of claim 11, wherein the mapping data structure comprises a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware logic is to manage the zone-to-block set data structure.
19. The memory controller of claim 12, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory device, wherein the hardware logic is to manage the write sequence data structure.
18. The processing device of claim 11, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory sub-system, wherein the hardware logic is to manage the write sequence data structure.
20. A method comprising:
identifying, by a processing device coupled to a memory device, a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA;
determining a zone identifier (ID) associated with the LTU;
retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and
performing, by the processing device, using the metadata, a memory access operation specified by the memory access request.
20. A method comprising:
storing, by a processing device of a memory sub-system within a system tag data structure, a system tag comprising a logical transfer unit (LTU) identifier corresponding to an LTU, wherein the LTU comprises a subset of a plurality of sequential logical block addresses (LBAs), wherein one of the subset is an LBA of a read request;
mapping, within a mapping data structure of the memory sub-system, a zone of an LBA space to a physical address space of the memory sub-system, wherein the zone comprises the plurality of sequential LBAs that are sequentially mapped to a plurality of sequential physical addresses;
retrieving, by a hardware accelerator of the processing device, the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure;
determining, by the hardware accelerator, a zone identifier (ID) based on the LTU identifier;
indexing, by the hardware accelerator using at least one of the zone ID or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and
storing, by the hardware accelerator, the metadata in the system tag data structure in association with the system tag.
The double patenting rejection above applies to claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1, hereinafter Park 2).
As per claim 1,
1. A system comprising: a memory device; and a processing device coupled to the memory device, the processing device to perform operations comprising: [Park teaches a system comprising a processor of a controller and non-volatile memory device (para. 33, 51; figs. 1, 3 and associated paragraphs)] identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA; [Park teaches L2P segments (LTU) that may comprise mappings between sequential LBAs and PBAs and also teaches L1 segments (zones) including a plurality of L2P segments (para. 45-48, 55, 84; figs. 3-4, 8 and associated paragraphs); Park teaches caching mapping segments for processing read requests, and, when receiving an LBA through a read request, determining whether the L2P segment containing the LBA is cached (para. 74-76, 81)] determining a zone identifier (ID) associated with the LTU; retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and performing, using the metadata, a memory access operation specified by the memory access request. [Responsive to the L2P segment or L1 segment comprising the L2P segment not being cached, a physical address at which the L1 segment comprising the L2P segment is stored may be determined for retrieving the L1 segment and the L2P segment from nonvolatile memory (para. 77-79; see para. 48 indicating index (ID) of L1 segment mapped to physical address at which the L1 segment is stored), where the L2P segment may also comprise metadata; Park teaches a map table, in non-volatile memory device, comprising the L2P segments and L1 segments (para. 43-48)]
Park does not explicitly disclose, but Park 2 discloses:
the LTU identifier [Park teaches an index of an L2P segment indicating physical address storing the L2P segment, but does not explicitly provide structure to the index (Park: para. 47); Park 2 teaches representing a map segment using start-logical address and end-logical address of the logical address area for each map segment (Park 2: para. 33, 232; fig. 12 and associated paragraphs); while Park does not provide for end-logical address, it does provide for head LBA corresponding to each respective L2P segment (Park: para. 56, 93; fig. 8 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts provided with disclosures of Park, directed towards L2P segments having respective index and head LBA, and disclosures by Park 2, directed towards to using start logical address and end logical address for referencing a map segment, to provide for a combination where a head LBA for a map segment may be used as an identifier for the map segment in order to provide for simplified referencing of respective map segments; where a L2P segment (metadata) necessarily provides a mapping between its head LBA and a physical address (see Park: 45)]
Park and Park 2 are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park and Park 2, to modify the disclosures by Park to include disclosures by Park 2 since both they both teach data storage and memory access, wherein Park 2 is directed towards more efficient reading of map data for processing requests (para. 5). Therefore, it would be applying a known technique (referencing a map segment using its start and logical addresses) to a known device (memory device having L2P segments with respective index and head address) ready for improvement to yield predictable results (using a head LBA of an L2P segment as an identifier for the L2P segment in order to provide for simplified referencing of respective map segments). MPEP 2143
As per claim 12,
12. A memory controller comprising: hardware logic coupled to a memory device, the hardware logic to perform operations comprising: [Park teaches a system comprising a processor of a controller and non-volatile memory device (para. 33, 51; figs. 1, 3 and associated paragraphs; see para. 51 providing for instructions/algorithms such as firmware)] identifying a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA; [Park teaches L2P segments (LTU) that may comprise mappings between sequential LBAs and PBAs and also teaches L1 segments (zones) including a plurality of L2P segments (para. 45-48, 55, 84; figs. 3-4, 8 and associated paragraphs); Park teaches caching mapping segments for processing read requests, and, when receiving an LBA through a read request, determining whether the L2P segment containing the LBA is cached (para. 74-76, 81)] determining a zone identifier (ID) associated with the LTU; retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and performing, using the metadata, a memory access operation specified by the memory access request. [Responsive to the L2P segment or L1 segment comprising the L2P segment not being cached, a physical address at which the L1 segment comprising the L2P segment is stored may be determined for retrieving the L1 segment and the L2P segment from nonvolatile memory (para. 77-79; see para. 48 indicating index (ID) of L1 segment mapped to physical address at which the L1 segment is stored), where the L2P segment may also comprise metadata; Park teaches a map table, in non-volatile memory device, comprising the L2P segments and L1 segments (para. 43-48)]
Park does not explicitly disclose, but Park 2 discloses:
the LTU identifier [Park teaches an index of an L2P segment indicating physical address storing the L2P segment, but does not explicitly provide structure to the index (Park: para. 47); Park 2 teaches representing a map segment using start-logical address and end-logical address of the logical address area for each map segment (Park 2: para. 33, 232; fig. 12 and associated paragraphs); while Park does not provide for end-logical address, it does provide for head LBA corresponding to each respective L2P segment (Park: para. 56, 93; fig. 8 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts provided with disclosures of Park, directed towards L2P segments having respective index and head LBA, and disclosures by Park 2, directed towards to using start logical address and end logical address for referencing a map segment, to provide for a combination where a head LBA for a map segment may be used as an identifier for the map segment in order to provide for simplified referencing of respective map segments; where a L2P segment (metadata) necessarily provides a mapping between its head LBA and a physical address (see Park: 45)]
Park and Park 2 are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park and Park 2, to modify the disclosures by Park to include disclosures by Park 2 since both they both teach data storage and memory access, wherein Park 2 is directed towards more efficient reading of map data for processing requests (para. 5). Therefore, it would be applying a known technique (referencing a map segment using its start and logical addresses) to a known device (memory device having L2P segments with respective index and head address) ready for improvement to yield predictable results (using a head LBA of an L2P segment as an identifier for the L2P segment in order to provide for simplified referencing of respective map segments). MPEP 2143
As per claim 20,
20. A method comprising: identifying, by a processing device coupled to a memory device, [Park teaches a system comprising a processor of a controller and non-volatile memory device (para. 33, 51; figs. 1, 3 and associated paragraphs; see para. 51 providing for instructions/algorithms such as firmware)] a logical transfer unit (LTU) corresponding to a logical block address (LBA) specified by a memory access request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of a plurality of zones of an LBA space of the memory device, wherein one of the subset is the LBA; [Park teaches L2P segments (LTU) that may comprise mappings between sequential LBAs and PBAs and also teaches L1 segments (zones) including a plurality of L2P segments (para. 45-48, 55, 84; figs. 3-4, 8 and associated paragraphs); Park teaches caching mapping segments for processing read requests, and, when receiving an LBA through a read request, determining whether the L2P segment containing the LBA is cached (para. 74-76, 81)] determining a zone identifier (ID) associated with the LTU; retrieving, from a mapping data structure that maps the zone to a subset of a physical address space of the memory device, using the zone ID, metadata that specifies a mapping between the LTU identifier and a physical address of the subset of the physical address space; and performing, by the processing device, using the metadata, a memory access operation specified by the memory access request. [Responsive to the L2P segment or L1 segment comprising the L2P segment not being cached, a physical address at which the L1 segment comprising the L2P segment is stored may be determined for retrieving the L1 segment and the L2P segment from nonvolatile memory (para. 77-79; see para. 48 indicating index (ID) of L1 segment mapped to physical address at which the L1 segment is stored), where the L2P segment may also comprise metadata; Park teaches a map table, in non-volatile memory device, comprising the L2P segments and L1 segments (para. 43-48)]
Park does not explicitly disclose, but Park 2 discloses:
the LTU identifier [Park teaches an index of an L2P segment indicating physical address storing the L2P segment, but does not explicitly provide structure to the index (Park: para. 47); Park 2 teaches representing a map segment using start-logical address and end-logical address of the logical address area for each map segment (Park 2: para. 33, 232; fig. 12 and associated paragraphs); while Park does not provide for end-logical address, it does provide for head LBA corresponding to each respective L2P segment (Park: para. 56, 93; fig. 8 and associated paragraphs); it would have been obvious for one of ordinary skill in the arts provided with disclosures of Park, directed towards L2P segments having respective index and head LBA, and disclosures by Park 2, directed towards to using start logical address and end logical address for referencing a map segment, to provide for a combination where a head LBA for a map segment may be used as an identifier for the map segment in order to provide for simplified referencing of respective map segments; where a L2P segment (metadata) necessarily provides a mapping between its head LBA and a physical address (see Park: 45)]
Park and Park 2 are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park and Park 2, to modify the disclosures by Park to include disclosures by Park 2 since both they both teach data storage and memory access, wherein Park 2 is directed towards more efficient reading of map data for processing requests (para. 5). Therefore, it would be applying a known technique (referencing a map segment using its start and logical addresses) to a known device (memory device having L2P segments with respective index and head address) ready for improvement to yield predictable results (using a head LBA of an L2P segment as an identifier for the L2P segment in order to provide for simplified referencing of respective map segments). MPEP 2143
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1).
As per claim 2, Park in view of Park 2 teaches claim 1 as shown above. It does not explicitly disclose, but Li teaches:
2. The system of claim 1, wherein the processing device comprises a hardware accelerator to perform the operations except for the identifying. [Park in view of Park 2 teaches loading L2P segments into a buffer comprising random access memory for read processing as well as mapping updates (see claim 1 above; Park: para. 72, 74, 64-65); Li teaches a hardware accelerator to which operations directed to logical-to-physical address table are offloaded to allow parallel processing while the controller performs write operations (para. 21, 26, 36-37; figs. 1, 5, and associated paragraphs); it would have been obvious for one of ordinary skill in the arts, provided with disclosures by Park in view of Park 2, providing for operations involving a mapping table such as updating a mapping table or locating/caching/managing mapping segments in association with read processing, and disclosures by Li, directed towards offloading operations directed to logical-to-physical tables to a hardware accelerator to allow parallel processing of a controller’s write operations, to provide for a combination where operations involving a mapping table such as locating/caching/managing of mapping segments in association with read or write commands may be offloaded to a hardware accelerator to provide for improved parallel processing and thus memory access efficiency]
Park, Park 2, and Li are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 with Li’s disclosures directed towards offloading operations involving a mapping table to a hardware accelerator. Doing so would allow for a reduction in processing latency (Li: para. 26).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1) in view of Young et al. (US 20120042114 A1).
As per claim 3, Park in view of Park 2 in view of Li teaches claim 2 as shown above. It does not explicitly disclose, but Young discloses:
The system of claim 2, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and a [Park in view of Park 2 in view of Li as shown above teaches caching L2P segments comprising portions of a mapping table in a random access memory buffer (Park: para. 64-65), hardware accelerator for offloading operations related to mapping tables, and a head LBA address for identifying a L2P segment (LTU identifier) (see claims 1-2 above)] system tag data structure, wherein the operations further comprise: storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and retrieving, by the hardware accelerator, the LTU identifier from the system tag in response to the processing device writing the system tag into the system tag data structure. [Young teaches a tag value indicative of a received command, where the tag value is stored in a memory with a corresponding mapping segment object handle, where the object handle is used to identify a particular corresponding mapping segment object (para. 32, 34, 37, 29; claim 12; figs. 2-4 and associated paragraphs; see claim 5 on applying the segment handle to output signal path (retrieving); see para. 37 providing any suitable lookup table mechanism may be utilized for associating tag value with a mapping segment object), where a tag value and the corresponding mapping segment object handle as stored may correspond to a system tag.]
Park, Park 2, and Li are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 with Li’s disclosures directed towards offloading operations involving a mapping table to a hardware accelerator. Doing so would allow for a reduction in processing latency (Li: para. 26).
Park, Park 2, Li, and Young are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li and Young, to modify the disclosures by Park in view of Park 2 in view of Li to include disclosures by Young since both they both teach data storage and memory access, wherein Young is directed towards improved overhead processing associated with address mapping (para. 8). Therefore, it would be applying a known technique (storing in a memory/table a tag associated with a received command along with a corresponding handle identifying a mapping segment) to a known device (memory device using random access memory for storing data including mapping segments identified by head LBA in association with a read request) ready for improvement to yield predictable results (memory device using random access memory for storing data including mapping segments identified by head LBA in association with a read request and a table comprising a tag value stored with a handle identifying the head LBA in order to provide for more efficient referencing of a mapping segment associated with a command received). MPEP 2143
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1) in view of Young et al. (US 20120042114 A1) in view of in view of Kershaw et al. (US 20080250217 A1).
As per claim 4, Park in view of Park 2 in view of Li in view of Young teaches claim 3 as shown above. It does not explicitly disclose, but Kershaw discloses:
4. The system of claim 3, wherein the hardware accelerator comprises one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of: a number of bits for the LTU identifier; an entry size for the mapping data structure; a location of the mapping data structure in the volatile memory device; or an ID mask in an entry that is set to invalid. [Park in view of Park 2 in view of Li in view of Young as shown above teaches caching L2P segments comprising portions of a mapping table in a random access memory buffer and hardware accelerator for offloading operations related to mapping tables (Park: para. 64-65; see claims 1, 3 above); Kershaw teaches configurable registers for configuring memory access settings, where the registers also include a translation table pointer specifying location of translation table data (para. 54-55, 38-39; claim 7; fig. 8 and associated paragraphs)]
Park, Park 2, Li, Young, and Kershaw are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li in view of Young and Kershaw, to modify the disclosures by Park in view of Park 2 in view of Li in view of Young to include disclosures by Kershaw since both they both teach data storage and memory access, wherein Kershaw is directed towards improved security in association with memory mapping and translation data (para. 16). Therefore, it would be applying a known technique (a configurable register storing location of mapping data) to a known device (memory device comprising random access memory comprising mapping segments and a hardware accelerator configured to offload operations associated with mapping table) ready for improvement to yield predictable results (memory device comprising random access memory comprising mapping segments managed by a hardware accelerator, the hardware accelerator comprising a configurable register comprising location of mapping segments in order to provide for improved efficiency and control over access to mapping information). MPEP 2143
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1) in view of Chang et al. (US 20110161562 A1).
As per claim 6, Park in view of Park 2 in view of Li teaches claim 2 as shown above. It does not explicitly disclose, but Chang discloses:
The system of claim 2, wherein the mapping data structure comprises: a logical-to-physical block map data structure to map the LTU identifier to a page map entry identifier, wherein the hardware accelerator is to manage the logical-to-physical block map data structure; and a page map data structure indexed by the page map entry identifier to provide a page identifier. [Park in view of Park 2 in view of Li as shown above teaches mapping of logical and physical addresses, head LBA comprising an LTU identifier, and a hardware accelerator for offloading operations related to mapping tables (see claims 1-2 above); Chang teaches tables used for mapping logical to physical addresses (para. 13) and discloses a portion of an LBA used as an index into a virtual block table for looking up address of a virtual page table (page map entry identifier) which corresponds to a block in the virtual block table, where the virtual page table is used to look up a physical page offset (page identifier) (para. 27-31; figs. 2-4 and associated paragraphs)]
Park, Park 2, and Li are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 with Li’s disclosures directed towards offloading operations involving a mapping table to a hardware accelerator. Doing so would allow for a reduction in processing latency (Li: para. 26).
Park, Park 2, Li, and Chang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 in view of Li with Chang’s disclosures directed towards multi-level address translation architecture. Doing so would allow for improved scalability and address translation efficiency (Chang: para. 8, 17, 42).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1) in view of Kotte et al. (US 20160342509 A1) in view of Vermeulen et al. (US 20100223438 A1).
As per claim 7, Park in view of Park 2 in view of Li teaches claim 2 as shown above. It does not explicitly disclose, but Kotte discloses:
7. The system of claim 2, wherein, to determine the zone ID, the operations performed by the hardware accelerator further comprise: and calculating the zone ID using the LTU identifier and the zone size value. [Park in view of Park 2 in view of Li as shown above teaches mapping of logical and physical addresses, head LBA comprising an LTU identifier, a L1 segment index (zone ID), and a hardware accelerator for offloading operations related to mapping tables (see claims 1-2 above); Kotte teaches a macro page including a plurality of virtual pages, where a logical address may be divided by the size of a macro page to obtain an index for accessing a mapping table portion corresponding to the macro page (para. 18, 77-78)]
Park in view of Park 2 in view of Li in view of Kotte does not explicitly disclose, but Vermeulen discloses:
accessing, within a firmware configurable register, a zone size value; [Vermeulen teaches a register comprising size of a memory region (para. 9-10)]
Park, Park 2, and Li are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 with Li’s disclosures directed towards offloading operations involving a mapping table to a hardware accelerator. Doing so would allow for a reduction in processing latency (Li: para. 26).
Park, Park 2, Li, and Kotte are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li and Kotte, to modify the disclosures by Park in view of Park 2 in view of Li to include disclosures by Kotte since both they both teach data storage and memory access, wherein Kotte is directed towards optimization of addressing mapping information (para. 14). Therefore, it would be applying a known technique (dividing an LBA by macro page size to determine an index for referencing mapping for the macro page) to a known device (memory device using a head LBA for referencing a L2P segment and having L1 segments (zones) comprising the segments; hardware accelerator for offloading mapping table related operations) ready for improvement to yield predictable results (memory device using a head LBA for referencing a L2P segment and having L1 segments (zones) comprising the segments, where a L1 segment (zone) associated with a L2P segment may be determined by a hardware accelerator by dividing the head LBA of the L2P segment by the size of a L1 segment in order to provide for faster determination of the corresponding L1 segment). MPEP 2143
Park, Park 2, Li, Kotte, and Vermeulen are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li in view of Kotte and Vermeulen, to modify the disclosures by Park in view of Park 2 in view of Li in view of Kotte to include disclosures by Vermeulen since both they both teach data storage and memory access, wherein Vermeulen is directed towards greater flexibility in management of regions in terms of size (para. 10). Therefore, it would be applying a known technique (maintaining size of a region in a register) to a known device (memory device utilizing a hardware accelerator for determining zone corresponding to a segment by dividing the head LBA of the segment by zone size) ready for improvement to yield predictable results (memory device utilizing a hardware accelerator for determining zone corresponding to a segment by dividing the head LBA of the segment by zone size as stored in a register in order to provide for improved referencing of the zone size and greater flexibility in adjusting zone size value being referenced). MPEP 2143
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 20180173420 A1) in view of Dong et al. (US 20070055844 A1).
As per claim 8, Park in view of Park 2 in view of Li teaches claim 2 as shown above. It does not explicitly disclose, but Dong discloses:
8. The system of claim 2, wherein operations performed by the hardware accelerator further comprise: calculating a hash value of the zone ID; and indexing into the mapping data structure using the hashed zone ID. [Park in view of Park 2 in view of Li as shown above teaches mapping of logical and physical addresses, a L1 segment index (zone ID), and a hardware accelerator for offloading operations related to mapping tables (see claims 1-2 above); Dong teaches a hash table structure being used for mapping a region ID to a mapping table (para. 20, 22-24; fig. 3A, 4, and associated paragraphs)]
Park, Park 2, Li, and Dong are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li and Dong, to modify the disclosures by Park in view of Park 2 in view of Li to include disclosures by Dong since both they both teach data storage and memory access, wherein Dong is directed towards improved address mapping (para. 1-2). Therefore, it would be applying a known technique (referencing a hash table using a region ID when accessing a mapping table) to a known device (memory device associating an index (zone ID) with a L1 segment and utilizing a hardware accelerator for offloading mapping table related operations) ready for improvement to yield predictable results (memory device utilizing a hardware accelerator for referencing a mapping table using a zone ID by using a hash table in order to provide for improved referencing speed). MPEP 2143
Claims 9, 11, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Liu et al. (US 20180046382 A1) in view of Parker et al. (US 11126378 B1).
As per claim 9, Park in view of Park 2 teaches claim 1 as shown above. It does not explicitly disclose, but Liu discloses:
9. The system of claim 1, wherein the mapping data structure comprises a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the operations further comprise managing the zone map data structure. [Park in view of Park 2 as shown above teaches mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment (see claims 1-2 above); Liu discloses a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses (para. 42), where it would have been obvious for one of ordinary skill in the arts to combine the disclosures by Park in view of Park 2, directed towards an L1 segment index (zone ID) for referencing the mapping segment, and disclosures by Liu, directed towards providing for mapping table mapping zone attributes/characteristics in association with zone physical addresses, to provide for a combination providing for a data structure including additional information where the L1 segment further comprises characteristics/attributes of the zone]
[Park in view of Park 2 in view of Liu does not explicitly disclose, but Parker discloses ZSLBA or zone ID for identifying a zone (col. 8, lines 50-60; col. 12, lines 5-14), states of zones (col. 3, lines 47-60; col. 9, lines 10-25, 54-67), next writable address of a zone as indicated by location of a write pointer in the zone (submission value) (col. 8, line 61 – col. 9, line 25) and zone capacity reflecting write pointer location in a full zone (completion value) (col. 9, line 54 – col. 10, line 28)), as well as storing of zone metadata (col. 9, lines 20-25; col. 10, lines 22-28)]
Park, Park 2, and Liu are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Liu, to modify the disclosures by Park in view of Park 2 to include disclosures by Liu since both they both teach data storage and memory access, wherein Liu is directed towards improved management of data as associated with logical blocks (para. 4). Therefore, it would be applying a known technique (a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses) to a known device (mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment) ready for improvement to yield predictable results (a data structure capable of including additional information such as characteristics/attributes of a zone). MPEP 2143
Park, Park 2, Liu, and Parker are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Liu and Parker, to modify the disclosures by Park in view of Park 2 in view of Liu to include disclosures by Parker since both they both teach data storage and memory access, wherein Parker is directed towards improved method for data storage (col. 1, lines 26-43). Therefore, it would be applying a known technique (tracking information including zone states and write pointer information) to a known device (mapping table comprising attributes or characteristics of respective zones) ready for improvement to yield predictable results (mapping table comprising attributes or characteristics of respective zones such as zone state and write pointer information for easier referencing of information associated with current state of the corresponding zone). MPEP 2143
As per claim 11, Park in view of Park 2 teaches claim 1 as shown above. It does not explicitly disclose, but Liu discloses:
11. The system of claim 1, wherein the mapping data structure comprises a write sequence data structure, indexed by the zone ID, to track a location of sequentially writing to physical addresses of the memory device, wherein the operations further comprise managing the write sequence data structure. [Park in view of Park 2 as shown above teaches mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment (see claims 1-2 above); Liu discloses a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses (para. 42), where it would have been obvious for one of ordinary skill in the arts to combine the disclosures by Park in view of Park 2, directed towards an L1 segment index (zone ID) for referencing the mapping segment, and disclosures by Liu, directed towards providing for mapping table mapping zone attributes/characteristics in association with zone physical addresses, to provide for a combination where the L1 segment further comprises characteristics/attributes of the zone]
[Park in view of Park 2 in view of Liu does not explicitly disclose, but Parker discloses write pointer of a zone for tracking sequential writes, i.e. the completion point of the prior write and the starting point of a subsequent write (col. 8, line 50 – col. 9, line 10)]
Park, Park 2, and Liu are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Liu, to modify the disclosures by Park in view of Park 2 to include disclosures by Liu since both they both teach data storage and memory access, wherein Liu is directed towards improved management of data as associated with logical blocks (para. 4). Therefore, it would be applying a known technique (a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses) to a known device (mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment) ready for improvement to yield predictable results (a data structure capable of including additional information such as characteristics/attributes of a zone). MPEP 2143
Park, Park 2, Liu, and Parker are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Liu and Parker, to modify the disclosures by Park in view of Park 2 in view of Liu to include disclosures by Parker since both they both teach data storage and memory access, wherein Parker is directed towards improved method for data storage (col. 1, lines 26-43). Therefore, it would be applying a known technique (tracking information including zone states and write pointer information) to a known device (mapping table comprising attributes or characteristics of respective zones) ready for improvement to yield predictable results (mapping table comprising attributes or characteristics of respective zones such as zone state and write pointer information for easier referencing of information associated with current state of the corresponding zone). MPEP 2143
Claim 19 is rejected for reasons similar to claim 11 above.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Chang et al. (US 20110161562 A1).
As per claim 10, Park in view of Park 2 teaches claim 1 as shown above. It does not explicitly disclose, but Chang discloses:
10. The system of claim 1, wherein the mapping data structure comprises: a zone-to-block set data structure to map the zone ID to a block set ID, wherein the operations further comprise managing the zone-to-block set data structure; and a block set map data structure to map the block set ID to block identifiers of physical blocks within the physical address space. [Park in view of Park 2 as shown above teaches mapping of logical and physical addresses and a L1 segment index (zone ID) (see claims 1-2 above); Chang teaches virtual regions and virtual blocks corresponding to respective physical regions and physical blocks, where a physical region may comprise a plurality of physical block sets (para. 26-31; fig. 2-4 and associated paragraphs); Chang teaches a virtual region table corresponding to a region may map addresses (block set ID) of virtual block tables (block set map data structure) each associated with a plurality of blocks within the region, and a virtual block table comprises addresses of virtual page tables each corresponding to a respective virtual block (mapping to block identifiers) in the virtual block table (para 27-31), where the virtual block table configured to be referenced via its address (block set ID) and used for determining address of virtual page tables (block identifiers) of respective blocks in the virtual block table may correspond to mapping; where Park in view of Park 2 as shown above teaches L1 segment index (zone ID) corresponding to address of the L1 segment (Park: para. 48) and Chang as shown above teaches referencing address of hierarchical mapping structures (e.g. virtual block table), it would have been obvious for one of ordinary skill in the arts to combines the teachings above for a combination where the L1 segment index (zone ID) is used to reference the virtual region table address which contains the virtual block table addresses (mapping zone ID to block set ID) in order to provide for greater flexibility and storage of mapping structure]
Park, Park 2, and Chang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 with Chang’s disclosures directed towards multi-level address translation architecture. Doing so would allow for improved scalability and address translation efficiency (Chang: para. 8, 17, 42 ).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Young et al. (US 20120042114 A1).
As per claim 13, Park in view of Park 2 teaches claim 12 as shown above. It does not explicitly disclose, but Young discloses:
13. The memory controller of claim 12, further comprising a volatile memory device configured to store the mapping data structure, the metadata, and [Park in view of Park 2 in view of Li as shown above teaches caching L2P segments comprising portions of a mapping table in a random access memory buffer (Park: para. 64-65) and a head LBA address for identifying a L2P segment (see claim 12 above)] a system tag data structure, wherein the operations further comprise: storing a system tag, which contains the LTU identifier for the LTU, in the system tag data structure; and retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure. [Young teaches a tag value indicative of a received command, where the tag value is stored in a memory with a corresponding mapping segment object handle, where the object handle is used to identify a particular corresponding mapping segment object (para. 32, 34, 37, 29; claim 12; figs. 2-4 and associated paragraphs; see claim 5 on applying the segment handle to output signal path (retrieving); see para. 37 providing any suitable lookup table mechanism may be utilized for associating tag value with a mapping segment object), where a tag value and the corresponding mapping segment object handle as stored may correspond to a system tag.]
Park, Park 2, and Young are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Young, to modify the disclosures by Park in view of Park 2 to include disclosures by Young since both they both teach data storage and memory access, wherein Young is directed towards improved overhead processing associated with address mapping (para. 8). Therefore, it would be applying a known technique (storing in a memory/table a tag associated with a received command along with a corresponding handle identifying a mapping segment) to a known device (memory device using random access memory for storing data including mapping segments identified by head LBA in association with a read request) ready for improvement to yield predictable results (memory device using random access memory for storing data including mapping segments identified by head LBA in association with a read request and a table comprising a tag value stored with a handle identifying the head LBA in order to provide for more efficient referencing of a mapping segment associated with a command received). MPEP 2143
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Li et al. (US 9946462 B1, hereinafter Li 2) in view of Chang et al. (US 20110161562 A1).
As per claim 15, Park in view of Park 2 teaches claim 12 as shown above. It does not explicitly disclose, but Li 2 discloses:
15. The memory controller of claim 12, wherein the mapping data structure comprises:
a logical-to-physical block map data structure to map the LTU identifier to a die identifier, a block identifier, and a page map entry identifier, wherein the hardware logic is to manage the logical-to-physical block map data structure; and [Park in view of Park 2 as shown above teaches LTU identifier comprising a head LBA address (see claim 12 above), but it does not explicitly disclose die identifier and block identifier. Li 2 discloses a memory storing a mapping table for mapping LBA to physical addresses and comprising die address, block address, and page address (col. 3, lines 3-18; col. 8, lines 46-64; col. 18, lines 9-20; figs. 1, 2, 8, and associated paragraphs)]
Park, Park 2, and Li 2 are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Li 2, to modify the disclosures by Park in view of Park 2 to include disclosures by Li 2 since they both teach data storage, wherein Li 2 is directed towards improved space efficiency in storing mapping data (col. 3, lines 10-18). Therefore, it would be applying a known technique (mapping table comprising die, block, and page addresses) to a known device (mapping table storing logical to physical mapping and head LBA identifying a mapping segment) ready for improvement to yield predictable results (mapping table storing logical to physical mapping and comprising die address, block address, and page address to provide for improved speed of accessing physical addresses). MPEP 2143
Park in view of Park 2 in view of Li 2 does not explicitly disclose, but Chang discloses:
a page map entry identifier; a page map data structure indexed by the page map entry identifier to provide a page identifier. [Chang teaches a system maintaining a three-level address translation architecture comprising virtual region table, virtual block table, and virtual page table (para. 27-31; figs. 2-4 and associated paragraphs)]
Park, Park 2, Li 2, and Chang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Li 2 and Chang, to modify the disclosures by Park in view of Park 2 in view of Li 2 to include disclosures by Chang since they both teach data storage, wherein Chang is directed towards improved scalability of memory access (para. 3-8). Therefore, it would be applying a known technique (multi-level address translation architecture comprising tables corresponding to region, block, and page) to a known device (mapping table indicating physical addresses corresponding to logical addresses, wherein the physical address may include die address, block address, and page address) ready for improvement to yield predictable results (mapping table indicating physical addresses corresponding to logical addresses, wherein the mapping table may comprise a multi-level structure for indicating physical addresses including tables for die address, block address, and page address to provide for faster address referencing). MPEP 2143
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Kershaw et al. (US 20080250217 A1).
As per claim, Park in view of Park 2 teaches claim 12 as shown above. It does not explicitly disclose, but Kershaw discloses:
16. The memory controller of claim 12, further comprising one or more registers to maintain a configuration data structure, wherein the configuration data structure is to store at least one of: a number of bits for the LTU identifier; an entry size for the mapping data structure; or a location in memory of the mapping data structure. [Kershaw teaches configurable registers for configuring memory access settings, where the registers also include a translation table pointer specifying location of translation table data (para. 54-55, 38-39; claim 7; fig. 8 and associated paragraphs)]
Park, Park 2, and Kershaw are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Kershaw, to modify the disclosures by Park in view of Park 2 to include disclosures by Kershaw since both they both teach data storage and memory access, wherein Kershaw is directed towards improved security in association with memory mapping and translation data (para. 16). Therefore, it would be applying a known technique (a configurable register storing location of mapping data) to a known device (memory device comprising a mapping table) ready for improvement to yield predictable results (memory device comprising a mapping table and a configurable register comprising location of mapping table in order to provide for improved efficiency and control over access to mapping information). MPEP 2143
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Kotte et al. (US 20160342509 A1) in view of Vermeulen et al. (US 20100223438 A1).
As per claim 17, Park in view of Park 2 in view teaches claim 12 as shown above. It does not explicitly disclose, but Kotte discloses:
17. The memory controller of claim 12, wherein, to determine the zone ID, the operations further comprise: calculating the zone ID using the LTU identifier and the zone size value. [Park in view of Park 2 as shown above teaches mapping of logical and physical addresses, head LBA comprising an LTU identifier, a L1 segment index (zone ID) (see claim 12 above); Kotte teaches a macro page including a plurality of virtual pages, where a logical address may be divided by the size of a macro page to obtain an index for accessing a mapping table portion corresponding to the macro page (para. 18, 77-78)]
Park in view of Park 2 in view of Kotte does not explicitly disclose, but Vermeulen discloses:
accessing, within a firmware configurable register, a zone size value; and [Vermeulen teaches a register comprising size of a memory region (para. 9-10)]
Park, Park 2, and Kotte are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Kotte, to modify the disclosures by Park in view of Park 2 to include disclosures by Kotte since both they both teach data storage and memory access, wherein Kotte is directed towards optimization of addressing mapping information (para. 14). Therefore, it would be applying a known technique (dividing an LBA by macro page size to determine an index for referencing mapping for the macro page) to a known device (memory device using a head LBA for referencing a L2P segment and having L1 segments (zones) comprising the segments) ready for improvement to yield predictable results (memory device using a head LBA for referencing a L2P segment and having L1 segments (zones) comprising the segments, where a L1 segment (zone) associated with a L2P segment may be determined by dividing the head LBA of the L2P segment by the size of a L1 segment in order to provide for faster determination of the corresponding L1 segment). MPEP 2143
Park, Park 2, Kotte, and Vermeulen are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Kotte and Vermeulen, to modify the disclosures by Park in view of Park 2 in view of Kotte to include disclosures by Vermeulen since both they both teach data storage and memory access, wherein Vermeulen is directed towards greater flexibility in management of regions in terms of size (para. 10). Therefore, it would be applying a known technique (maintaining size of a region in a register) to a known device (memory device determining zone corresponding to a segment by dividing the head LBA of the segment by zone size) ready for improvement to yield predictable results (memory device determining zone corresponding to a segment by dividing the head LBA of the segment by zone size as stored in a register in order to provide for improved referencing of the zone size and greater flexibility in adjusting zone size value being referenced). MPEP 2143
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190155723 A1) in view of Park (US 20200401345 A1; Park 2) in view of Liu et al. (US 20180046382 A1) in view of Parker et al. (US 11126378 B1) in view of Chang et al. (US 20110161562 A1).
As per claim 18, Park in view of Park 2 teaches claim 12 as shown above. It does not explicitly disclose, but Liu discloses:
18. The memory controller of claim 12, wherein the mapping data structure comprises:
a zone map data structure to map the zone ID to a zone state, a zone write pointer submission value, and a zone write pointer completion value, and wherein the hardware logic is to manage the zone map data structure; and [Park in view of Park 2 as shown above teaches mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment (see claim 12 above); Liu discloses a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses (para. 42), where it would have been obvious for one of ordinary skill in the arts to combine the disclosures by Park in view of Park 2, directed towards an L1 segment index (zone ID) for referencing the mapping segment, and disclosures by Liu, directed towards providing for mapping table mapping zone attributes/characteristics in association with zone physical addresses, to provide for a combination providing for a data structure including additional information where the L1 segment further comprises characteristics/attributes of the zone]
[Park in view of Park 2 in view of Liu does not explicitly disclose, but Parker discloses ZSLBA or zone ID for identifying a zone (col. 8, lines 50-60; col. 12, lines 5-14), states of zones (col. 3, lines 47-60; col. 9, lines 10-25, 54-67), next writable address of a zone as indicated by location of a write pointer in the zone (submission value) (col. 8, line 61 – col. 9, line 25) and zone capacity reflecting write pointer location in a full zone (completion value) (col. 9, line 54 – col. 10, line 28)), as well as storing of zone metadata (col. 9, lines 20-25; col. 10, lines 22-28)]
Park, Park 2, and Liu are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 and Liu, to modify the disclosures by Park in view of Park 2 to include disclosures by Liu since both they both teach data storage and memory access, wherein Liu is directed towards improved management of data as associated with logical blocks (para. 4). Therefore, it would be applying a known technique (a zone mapping table which maps zone attributes/characteristics as a function of zone physical addresses) to a known device (mapping of logical and physical addresses and L1 segment indexes (zone ID) pointing to location of the segment) ready for improvement to yield predictable results (a data structure capable of including additional information such as characteristics/attributes of a zone). MPEP 2143
Park, Park 2, Liu, and Parker are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Park in view of Park 2 in view of Liu and Parker, to modify the disclosures by Park in view of Park 2 in view of Liu to include disclosures by Parker since both they both teach data storage and memory access, wherein Parker is directed towards improved method for data storage (col. 1, lines 26-43). Therefore, it would be applying a known technique (tracking information including zone states and write pointer information) to a known device (mapping table comprising attributes or characteristics of respective zones) ready for improvement to yield predictable results (mapping table comprising attributes or characteristics of respective zones such as zone state and write pointer information for easier referencing of information associated with current state of the corresponding zone). MPEP 2143
Park in view of Park 2 in view of Liu in view of Parker does not explicitly disclose, but Chang discloses:
a zone-to-block set data structure to map the zone ID to a block set ID, wherein the hardware logic is to manage the zone-to-block set data structure. [Park in view of Park 2 in view of Liu in view of Parker as shown above teaches mapping of logical and physical addresses and a L1 segment index (zone ID) (see claim 12 and the rejection above); Chang teaches virtual regions and virtual blocks corresponding to respective physical regions and physical blocks, where a physical region may comprise a plurality of physical block sets (para. 26-31; fig. 2-4 and associated paragraphs); Chang teaches a virtual region table corresponding to a region may map addresses (block set ID) of virtual block tables (block set map data structure) each associated with a plurality of blocks within the region, and a virtual block table comprises addresses of virtual page tables each corresponding to a respective virtual block (mapping to block identifiers) in the virtual block table (para 27-31), where the virtual block table configured to be referenced via its address (block set ID) and used for determining address of virtual page tables (block identifiers) of respective blocks in the virtual block table may correspond to mapping; where Park in view of Park 2 as shown above teaches L1 segment index (zone ID) corresponding to address of the L1 segment (Park: para. 48) and Chang as shown above teaches referencing address of hierarchical mapping structures (e.g. virtual block table), it would have been obvious for one of ordinary skill in the arts to combines the teachings above for a combination where the L1 segment index (zone ID) is used to reference the virtual region table address which contains the virtual block table addresses (mapping zone ID to block set ID) in order to provide for greater flexibility and storage of mapping structure]
Park, Park 2, Liu, Parker, and Chang are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Park in view of Park 2 in view of Liu in view of Parker with Chang’s disclosures directed towards multi-level address translation architecture. Doing so would allow for improved scalability and address translation efficiency (Chang: para. 8, 17, 42 ).
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims in a manner which also overcomes the rejection pursuant to 112(b) and the double patenting rejections as indicated above.
With respect to claim 5, “… storing the metadata in the system tag data structure in association with the system tag; and sending a system tag identifier for the system tag to a command generation processor of the processing device, and wherein the command generation processor of the processing device is further to generate a read command using the metadata stored with the system tag in the system tag data structure.” in conjunction with the other limitations of the claim and the limitations of the base claim and the intervening claims, are not disclosed by the prior art of record.
The closest prior arts of record are Park et al. (US 20190155723 A1), Park (US 20200401345 A1; Park 2), Li et al. (US 20180173420 A1), Young et al. (US 20120042114 A1), Yen et al. (US 20110296106 A1), Blomquist et al. (US 20060224822 A1), and Tamura et al. (US 20090327598 A1).
Park teaches caching mapping segments associated with a command received. Park teaches identifying a mapping segment based on first and last logical addresses. Young teaches a hardware accelerator for offloading mapping table-related operations. Young teaches a tag associated with a mapping segment identifier. Yen teaches a transmitting data to a storage medium according to a command tag included in a data and a mapping table. Blomquist teaches associating with a tag with a data type and mapping the tag to a data identifier. Tamura teaches a command management table comprising command entries for write commands and a zone number to which the LBA associated with the command belongs.
However, the prior arts of record, neither individually nor in combination, teaches, in association with identifying an logical transfer unit (LTU) based on an LBA of a read request, using the LTU to determine a corresponding zone ID, using the zone ID to fetch from a mapping table a metadata which maps an identifier for the LTU to a physical address, storing a system tag containing the LTU identifier in a system tag data structure in a volatile memory, also storing the metadata in the system tag structure in association with the system tag, and sending a system tag identifier of the system tag to a command generation processor to further generate a read command using the metadata stored in the system tag.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim and the intervening claims, the claim as a whole.
With respect to claim 14, “… retrieving the LTU identifier from the system tag in response to the hardware logic writing the system tag into the system tag data structure; determining a hash value of the zone ID; indexing, using at least one of the hash value or the LTU identifier, into the mapping data structure to retrieve the metadata; and storing the metadata in the system tag data structure in association with the system tag.” in conjunction with the other limitations of the claim and the limitations of the base claim and the intervening claims, are not disclosed by the prior art of record.
The closest prior arts of record are Park et al. (US 20190155723 A1), Park (US 20200401345 A1; Park 2), Li et al. (US 20180173420 A1), Young et al. (US 20120042114 A1), Yen et al. (US 20110296106 A1), Blomquist et al. (US 20060224822 A1), and Tamura et al. (US 20090327598 A1).
Park teaches caching mapping segments associated with a command received. Park teaches identifying a mapping segment based on first and last logical addresses. Young teaches a hardware accelerator for offloading mapping table-related operations. Young teaches a tag associated with a mapping segment identifier. Yen teaches a transmitting data to a storage medium according to a command tag included in a data and a mapping table. Blomquist teaches associating with a tag with a data type and mapping the tag to a data identifier. Tamura teaches a command management table comprising command entries for write commands and a zone number to which the LBA associated with the command belongs.
However, the prior arts of record, neither individually nor in combination, teaches, in association with identifying an logical transfer unit (LTU) based on an LBA of a read request, using the LTU to determine a corresponding zone ID, using the zone ID to fetch from a mapping table a metadata which maps an identifier for the LTU to a physical address, storing a system tag containing the LTU identifier in a system tag data structure in a volatile memory, determining a hash value of the zone ID, using the zone ID or the LTU identifier into the mapping table for retrieving the metadata, and storing the metadata in the system tag data structure in association with the system tag.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim and the limitations of the base claim and the intervening claims, the claim as a whole.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Byun et al. (US 20200301852 A1) teaches uploading segments belonging to partial logical address groups for caching in host memory.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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