DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banerjee et al. (US 2011/0073942; hereinafter Banerjee).
Regarding claim 11:
Banerjee discloses a semiconductor device (see Fig. 2) for driving a display (the limitation “for driving a display” is not given patentable weight because it is in the preamble) comprising:
a first conductivity type base layer (see Fig. 2; P substrate 20 and N well 12 correspond to a first conductivity type base layer);
a second conductivity type doping area disposed on the first conductivity type base layer (see Fig. 2; P well 22 is a second conductivity type doping area);
a source area disposed on the second conductivity type doping area (see Fig. 2; source 26);
a drain area disposed on the first conductivity type base layer (see Fig. 2; drain 11);
a gate insulating film disposed between the source area and the drain area (see Fig. 2; filed oxide layer 25 is a gate insulating film);
a gate electrode disposed on the gate insulating film (see Fig. 2; gate 15); and
wherein the second conductivity type doping area comprises an active corner cut area in a corner area facing the drain area in a plan view (see Figs. 1 and 4; the corner 41 is facing the drain 11; Fig. 4 shows the corner 41 is curved; the curved corner is the result of a corner being cut).
Regarding claim 12:
Banerjee discloses the semiconductor device according to claim 11, wherein an active area comprises the second conductivity type doping area and the source area (see Figs. 1-2), and wherein the active area comprises a first active area at a first region vertically overlapping the gate electrode (see Fig. 4; the active area overlaps the gate electrode 15 in the center region) and a second active area 18 at a second region laterally overlapping the active corner cut area (see Fig. 4; the active area 18 laterally overlaps the corner region 41).
Regarding claim 13:
Banerjee discloses the semiconductor device according to claim 12, wherein a width of the first active area is larger than a width of the second active area (see Fig. 4; the width of the active area 18 at the center is larger than the width of the active area 18 at the corner area).
Regarding claim 14:
Banerjee discloses the semiconductor device according to claim 12, wherein the active corner cut area comprises a first active corner cut area disposed at an upper edge of the second active area facing the drain area (see Fig. 4; the corner 41 is at the upper edge of the second active area facing the drain area), and a second active corner cut area disposed at a lower edge of the second active area facing the drain area (see Fig. 1; the lower corner 41 is at the lower edge of the second active area facing the drain area; the lower corner 41 is not shown in the Fig. 4, but the lower corner 41 is also curved like the upper corner 41 to maintain the electric field distribution needed to support high-voltages; see paragraph [0026]).
Regarding claim 15:
Banerjee discloses the semiconductor device according to claim 12, wherein a distance from the first active area to the drain area is shorter than a distance from the second active area to the drain area (see Fig. 1; when the corners 41 is replaced by the curved corner as shown in Fig. 4, the distance from the first active area to the drain area is shorter than a distance from the second active area to the drain area).
Regarding claim 16:
Banerjee discloses the semiconductor device according to claim 12, wherein a distance from the first active area to the outside of the gate electrode in a direction of the drain area is shorter than a distance from the second active area to the gate electrode in a direction of the drain area (see Fig. 4; the distance from the center area of the active area 18 to the edge of the gate electrode 15 is shorter than the distance from the curved corner 41 to the edge of the gate electrode 15).
Regarding claim 19:
Banerjee discloses the semiconductor device according to claim 11, wherein the active area does not comprise the active corner cut area in the corner area facing the source area (see Figs. 1 and 4; only the corners closest to the drain is modified to be curved).
Regarding claim 20:
Banerjee discloses a display driving device (see paragraph [0004]; the timing and control circuit is a display driving device) comprising the semiconductor device for driving the display according to claim 1 (see claim 11 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banerjee in view of Wu et al. (US 2023/0061900; hereinafter Wu).
Regarding claim 1:
Banerjee discloses a semiconductor device (see Fig. 2) for driving a display (the limitation “for driving a display” is not given patentable weight because it is in the preamble) comprising:
a first conductivity type base layer (see Fig. 2; P substrate 20 and N well 12 correspond to a first conductivity type base layer);
a second conductivity type doping area disposed on the first conductivity type base layer (see Fig. 2; P well 22 is a second conductivity type doping area);
a source area disposed on the second conductivity type doping area (see Fig. 2; source 26);
a drain area disposed on the first conductivity type base layer (see Fig. 2; drain 11);
a gate insulating film disposed between the source area and the drain area (see Fig. 2; filed oxide layer 25 is a gate insulating film);
a gate electrode disposed on the gate insulating film (see Fig. 2; gate 15); and
wherein an active area having the second conductivity type doping area and the source area comprises an active corner cut area in a corner area facing the drain area (see Figs. 1, 2 and 4; also see paragraph [0025]; Fig. 4 shows the corner region of the active area 18 is curved; the curved area is interpreted as an active corner cut area; also as shown in Fig. 1, the active area 18 includes corner area that is facing the drain 11) .
Banerjee does not disclose one or more device isolating areas disposed on the base layer.
However, in the same field of endeavor, Wu discloses a semiconductor device comprising:
one or more device isolating areas disposed on the base layer (see Fig. 9; isolation features structures 104).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the semiconductor device of Banerjee to include one or more device isolating areas disposed on the base layer as taught by Wu. One of ordinary skill in the art would have been motivated to do this because isolation feature structure is formed in the substrate to define and electrically isolate various active regions (see Wu, paragraph [0017]).
Regarding claim 2:
Banerjee and Wu disclose all the features in claim 1. Banerjee further discloses the semiconductor device, wherein the active area comprises a first active area at a center of the gate electrode (see Figs. 1-2; the first active area corresponds to center area of the active area 18) and a second active area at the active corner cut area (see Figs. 1 and 4; the second active area corresponds to the corner area of the active area 18).
Regarding claim 3:
Banerjee and Wu disclose all the features in claim 2. Banerjee further discloses the semiconductor device, wherein a width of the first active area is larger than a width of the second active area (see Fig. 4; the width of the active area 18 at the center is larger than the width of the active area 18 at the corner area).
Regarding claim 4:
Banerjee and Wu disclose all the feature in claim 2. Banerjee further discloses the semiconductor device, wherein the active corner cut area comprises a first active corner cut area disposed at an upper edge of the second active area facing the drain area (see Fig. 4; the corner 41 is at the upper edge of the second active area facing the drain area), and a second active corner cut area disposed at a lower edge of the second active area facing the drain area (see Fig. 1; the lower corner 41 is at the lower edge of the second active area facing the drain area; the lower corner 41 is not shown in the Fig. 4, but the lower corner 41 is also curved like the upper corner 41 to maintain the electric field distribution needed to support high-voltages; see paragraph [0026]).
Regarding claim 5:
Banerjee and Wu disclose all the features in claim 2. Banerjee further discloses the semiconductor device, wherein a distance from the first active area to the drain area is shorter than a distance from the second active area to the drain area (see Fig. 1; when the corners 41 is replaced by the curved corner as shown in Fig. 4, the distance from the first active area to the drain area is shorter than a distance from the second active area to the drain area).
Regarding claim 6:
Banerjee and Wu disclose all the features in claim 2. Banerjee further discloses the semiconductor device, wherein a distance from the first active area to the outside of the gate electrode in a direction of the drain area is shorter than a distance from the second active area to the gate electrode in a direction of the drain area (see Fig. 4; the distance from the center area of the active area 18 to the edge of the gate electrode 15 is shorter than the distance from the curved corner 41 to the edge of the gate electrode 15).
Regarding claim 9:
Banerjee and Wu disclose all the features in claim 9. Banerjee further discloses the semiconductor device according to claim 1, wherein the active area does not comprise the active corner cut area in the corner area facing the source area (see Figs. 1 and 4; only the corners closest to the drain is modified to be curved).
Regarding claim 10:
Banerjee and Wu disclose all the features in claim 1. Banerjee further discloses a display driving device (see paragraph [0004]; the timing and control circuit is a display driving device) comprising the semiconductor device for driving the display according to claim 1 (see claim 1 above).
Claim(s) 7, 8, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banerjee in view of Wu as applied to claim 1 above, and further in view of Tegen et al. (CN115566051A; hereinafter Tegen).
Regarding claim 7:
Banerjee and Wu disclose all the features in claim 7. Banerjee and Wu do not teach the semiconductor device, wherein the active corner cut area comprises a right-angled triangle shape.
However, in the same field of endeavor, Tegen discloses a semiconductor device, wherein the active corner cut area comprises a right-angled triangle shape (see Fig. 1B and page 9, 7th paragraph; “contour of the outermost elongated groove 15 "and the contour of the edge trench 22 are formed so as to reduce the possibility of breakdown in the region of the transistor device and to increase the breakdown voltage”; region 22/23 are part of the active cell field of the transistor device; the corner of the region 22/23 comprise a right-angled triangle shape).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the semiconductor device of Banerjee and Wu such that the active corner cut area comprises a right-angled triangle shape as taught by Tegen. One of ordinary skill in the art would have been motivated to do this because the design of the corner region of the edge termination region is optimized to avoid breakdown in the corner region (see Tegen, page 7, 5th paragraph).
Regarding claim 8:
Banerjee, Wu, and Tegen disclose all the features in claim 7. Tegen further discloses the semiconductor device, wherein the active corner cut area comprises a first side and a second side perpendicular to the first side of the active corner cut area (see Fig. 1B; the first side corresponds to the line extending from the outer side wall of the region 23, and the second side corresponds to the line extending from the outer side wall of the region 22).
Tegen discloses the claimed invention; however, Tegen does not specifically disclose the length of the first side and the length of the second side are the same. Nevertheless, before the effective filing date of the claimed invention, it would have been obvious to one having ordinary skill in the art to use equal length of the first side and the second side of the active corner cut area in order to avoid breakdown voltage distribution characteristic in the semiconductor device, where the claimed differences involved to the substitution of interchangeable or replaceable equivalents and the reason for the selection of one equivalent for another was not to solve an existent problem, such substitution has been judicially determined to have been obvious. In re Ruff, 118, USPQ, 343 (CCPA 1958). This supporting is based on a recognition that the claimed difference exist not a result of an attempt by applicant to solve a problem but merely amounts to selection of expedients known to the artisan of ordinary skill as design choices.
Regarding claims 17 and 18:
Claims 17 and 18 each recites similar limitations as in claims 7 and 8, respectively. Hence, claims 17 and 18 are rejected under the same reasons as discussed above in claims 7 and 8, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2023/0170417) discloses a high voltage semiconductor device comprising a gate filed plate between the gate electrode and the drain electrode to prevent an electric field from concentrating at an edge of the gate electrode.
Kudou et al. (US 2019/0080976) discloses a semiconductor device including at least one ring region of the second conductively type, wherein the shape of the four rounded corners of the ring prevent concentration of an electric field on the four corners.
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/LIXI C SIMPSON/Primary Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625