DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 7 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “control recording medium” of claim 7 encompasses software per se. A computer program may be statutory if it is claimed as a physical product, by reciting the program in conjunction with a “non-transitory computer readable medium.” The specification states that “the data storage unit 57 is a recording medium that stores a parameter necessary for implementing a predetermined function, a control recording medium, measurement biological data acquired from the measurement device 1, and the like. The data storage unit 57 includes, for example, a hard disk drive (HDD) or a semiconductor storage device (SSD)” recited in Paragraph 0077 and further states “The controller 58 implements a predetermined function by executing the control recording medium. Note that in the present embodiment, for example, management application software for an information terminal is installed in advance as a control recording medium in the data storage unit 57,”, which could indicate that the control recording medium is a software. The specification does not positively restrict the medium to only statutory embodiments, and under a broadest reasonable interpretation the medium might include signals (i.e. transitory propagating signals, carrier waves, etc.) and is thus directed to nonstatutory subject matter (see MPEP §2106; In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007); and the Director' s Memo Subject Matter Eligibility of Computer Readable Media, 1351 Off. Gaz. Pat. Office 212 (Feb. 23, 2010)). In order to overcome the rejection, Applicant(s) should amend “control recording medium” of claim 7 such that the program is a physical product in conjunction with the medium and the medium is non-transitory in nature, “non-transitory computer readable storage medium”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over “Okabe” (JP2012115544A) in view of “Kwon” (US2008256305A1) and “Kudo” (US 20130311685 A1).
Regarding claim 1.
Okabe teaches A measurement device (Paragraphs 0017 and 0020) comprising:
a first processor (sensor control unit 13) that performs measurement based on biological data obtained by a sensor (Paragraph 0021: “The sensor unit 10 has a function of sequentially measuring biological information”, “a sensor element 11, a processing circuit 12, and a sensor control unit 13 are provided as main circuit units. The sensor element 11 is an element that measures biological information from a living body test part. Here, the sensor element 11 includes a light emitting element and a light receiving element”, and Paragraph 0022: “The processing circuit 12 includes a signal processing circuit such as an A / D conversion circuit, and has a function of converting a measurement signal output from the sensor element 11 into biological information (data). The sensor control unit 13 includes a control circuit such as a microcomputer that executes information processing by executing a program”);
a second processor (wireless control unit 32) that performs wireless communication with an information terminal (external device 50) (Paragraph 0024: “The wireless unit 30 has a function of reading out biometric information from the memory unit 20 and wirelessly transmitting it, and a wireless module 31 is provided as a main circuit unit. The wireless module 31 is a circuit unit that intermittently performs wireless communication using a general-purpose wireless communication method such as Bluetooth or Zigbee, and a wireless control unit 32 is provided as a main processing unit.”, and Paragraph 0025: “The wireless control unit 32 includes a control circuit such as a microcomputer, and includes a control circuit such as a microcomputer that executes information processing by executing a program”, “A function of switching and selecting any one of the unselected buffer memories as a reading source of the biological information, and reading the biological information from the selected reading source buffer memories 21 and 22 and wirelessly transmitting them to the external device 50 It has a function”);
Okabe does not teach a memory connected to the second processor and inaccessible from the first processor, wherein the first processor
specifies an address of a write destination in the memory and
causes the second processor to write the biological data into the memory, and
specifies an address of a read source in the memory and
causes the second processor to read the biological data from the memory and transmit the biological data to the information terminal.
Kwon teaches a memory (Flash memory 300) connected to the second processor (second processor 200) (Paragraph 0042: “Flash memory 300 is coupled to second processor 200”) and inaccessible from the first processor (first processor 100) (Paragraph 0025: “First processor 100 communicates with second processor 200 via DRAM 400 without the use of external interfacing, thereby indirectly accessing flash memory 300. In this manner, when first processor 100 is coupled to DRAM 400, first processor 100 indirectly accesses flash memory 300 which is connected to second processor 200.” and Paragraph 0029: “This control command allows first processor 100 to indirectly access flash memory 300 by utilizing the shared memory area 11 and internal register 50. This is done even when only second processor 200 is coupled to flash memory 300”, and the Examiner notes that inaccessible, as best understood in light of the specification, means no direct access),
wherein the first processor specifies an address of a write destination in the memory (Paragraph 0042: “first processor 100 searches for a physical address corresponding to a logical address”, “first processor 100 writes, physical address of flash memory, write data size, address of shared memory area 11 (where write data is stored), and the write command in first mailbox area 52”, Paragraph 0044: “first processor 100 only handles the logical address of flash memory in the write operation, step S11 is skipped and the logical address of the flash memory is written in first mailbox area 52 in step S12. Second processor 200 searches for the physical address corresponding to the logical address based on the information from storage table area 110. Second processor 200 directly searches for an address map table allocated to the interior of flash memory 300.”, and Paragraph 0045: “first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52.”) and
causes the second processor to write the biological data into the memory (Paragraph 0042: “first processor 100 transmits an interrupt signal INTb.”, Paragraph 0043: “Second processor 200, which periodically checks semaphore area 51, determines whether the transmit INTb signal is received at step S14. If signal INTB is received, second processor has access permission after reading flag data of semaphore area 51 at step S15. Second processor 200 acquires a use priority for shared memory area 11 and reads the contents written to the first mailbox area 52 in step S16. In step S17, the data written to shared memory area 11 is read and the data is written to a corresponding physical address of the flash memory 300 based on the contents of data read from first mailbox area 52”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100 based on the contents read from first mailbox area 52”), and
specifies an address of a read source in the memory (Paragraph 0045: “first processor 100 searches for the physical address corresponding to the logical address referring to storage table area 110 of shared memory area 11. In step S22, first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52”) and
causes the second processor to read the biological data from the memory (Paragraph 0045: “First processor 100 transmits an interrupt signal INTb in step S23.”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100”) and
Kudo teaches the first processor (CTLa MTU 101a) causes the second processor (CTLb MTU 101b) to transmit the data to the information terminal (Host 2) (Paragraph 0042: “The CTLa comprises an MPU 101a, an MPU memory 102a, a DMA 103a, a HOST_I/F (I/F: abbreviation for interface, the same subsequently) 104a, a DRIVE_I/F 105a, and a management_I/F 106a. The same is true of the CTLb. The HOST_I/F 104a of the CTLa and the HOST_I/F 104b of the CTLb are each connected to the host 2 via the SAN 5.”, Paragraph 0059: “The request transmission program 207 a issues a request to or via the MPU 101 b of the external system controller 101 a for access to enable the configuration management program 201 a or basic I/O program 202 a to read or write to the SM12 b and the cache memory 13 b of the MPU memory 102 b of the external system controller 100 b and to start up the interfaces 104 b and 105 b and the DMA 103 b, This request is achieved as a result of the processor 101 a writing request information (commands and the like) in the communication area 14 b of the MPU memory 102 b of the external system controller via the bridge 108 and the MPU 101 b of the external system controller executing this command. ”, Paragraph 0109: “the basic I/O program starts the request transmission program 207 a in order to request the startup of the HOST_IF access program 210 b of the external system controller 100 b”, Paragraph 0113: “Upon receiving a response from the HOST_IF access program 210 a of the internal system controller 100 a which is the startup target in S1013 or receiving a response from the HOST_IF access program 210 b of the external system controller 100 b which is the startup target in S1014”, and Fig. 1) (the examiner note: Okabe teaches the data comprises the biological data above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe’s measurement device with Kwon’s indirect memory-access arrangement, in which the memory is coupled to the second processor and the first processor specifies read/write addresses and causes the second processor to perform the corresponding memory operations, because such an modification would have allowed multiple processors to use a single flash memory, thereby reducing memory cost and system size (Kwon, Abstract; Paragraph 0036).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe in view of Kwon by incorporating request-controlled interface arrangement, as taught by Kudo, because incorporating such an arrangement would have allowed the first processor to initiate data transmission through an interface controlled by the second processor (Kudo, Paragraph 0059,0109,0113). When applied to Okabe, the transmitted data would be Okabe’s biological data, and the interface would be the wireless interface of wireless control unit 32 communicating with external device 50 (Okabe, Paragraph 0024-0025, 0030).
Regarding claim 2, Okabe in view of Kwon and Kudo teaches the measurement device of claim 1 (see rejection claim 1 above).
Okabe teaches wherein the memory (memory unit 20) has an area allocated for the biological data (buffer memories 21/22) (Paragraph 0018: “the biometric information is sequentially measured and written to the buffer memory, and the biometric information is read from the buffer memory and transmitted wirelessly”, Paragraph 0022: “the sensor control unit 13 stores one of the buffer memories 21 and 22 of the memory unit 20 as a living body. It has a function of switching and selecting as an information writing destination,”, and Paragraph 0023: “The memory unit 20 includes a storage device such as a semiconductor memory, has a plurality of buffer memories 21 and 22, and has a function of temporarily storing biological information obtained by the sensor unit 10. “), and
However, Okabe does not teach the address of the write destination and the address of the read source are addresses in the area.
Kwon teaches the address of the write destination (physical address in flash memory 300) (Paragraph 0031: “FIG. 6 is an address map table illustrating the matching of physical addresses and logical addresses of flash memory 300. Address area LA1-LA8 indicates a logical address which is matched on a one to one basis with physical address area PA1-PA10”, Paragraph 0042: “first processor 100 searches for a physical address corresponding to the logical address of flash memory 300. In step S12, first processor 100 writes, physical address of flash memory, write data size, address of shared memory area 11 (where write data is stored), and the write command in first mailbox area 52”, and Paragraph 0043: “the data is written to a corresponding physical address of the flash memory 300 based on the contents of data read from first mailbox area 52.”) and
the address of the read source are addresses in the area (physical address in flash memory 300) (Paragraph 0045: “first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52. First processor 100 transmits an interrupt signal INTb in step S23. Data having a logic high ‘1’ in semaphore area 51 is changed to a logic low ‘0’ so that second processor 200 recognizes that first processor 100 has given access permission to the second processor.”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100 based on the contents read from first mailbox area 52”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe’s measurement device with Kwon’s indirect memory-access arrangement, in which the memory is coupled to the second processor and the first processor specifies read/write addresses and causes the second processor to perform the corresponding memory operations, because such an modification would have allowed multiple processors to use a single flash memory, thereby reducing memory cost and system size (Kwon, Abstract; Paragraph 0036).
Regarding claim 3, Okabe in view of Kwon and Kudo teaches the measurement device of claim 1 (see rejection claim 1 above).
Okabe teaches wherein the biological data is pulse wave data (Paragraph 0019: “the wireless biological information sensor 100 measures and transmits biological information composed of pulse wave data obtained by capturing a blood vessel volume change caused by blood inflow as a waveform from the body surface will be described as an example”, and Paragraph 0020: “a case where pulse waves are measured from a finger as biometric information and wirelessly transmitted will be described as an example.”).
Regarding claim 5, Okabe in view of Kwon and Kudo teaches the measurement device of claim 1 (see rejection claim 1 above).
Okabe does not teach wherein the memory is a nonvolatile memory.
Kwon teaches wherein the memory is a nonvolatile memory (Paragraph 0007: “Flash memories 301 and 302 may be a NOR type or NAND type. NOR flash memory or NAND flash memory is a nonvolatile memory having a transistor memory cell having a floating gate”, and Paragraph 0025: “Flash memory 300 is coupled to second processor 200”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe with Kwon’s nonvolatile flash memory, because incorporating nonvolatile flash memory would have allowed the biological data to retain stored regardless of the power state (Kwon, Paragraph 0007).
Regarding claim 6.
Okabe teaches A control method of a measurement device (Paragraph 0017) including a first processor (sensor control unit 13) that performs measurement based on biological data obtained by a sensor (Paragraph 0021: “The sensor element 11 is an element that measures biological information from a living body test part. Here, the sensor element 11 includes a light emitting element and a light receiving element.”, and Paragraph 0022: “The sensor control unit 13 includes a control circuit such as a microcomputer that executes information processing by executing a program’),
a second processor (wireless control unit 32) that performs wireless communication with an information terminal (external device 50) (Paragraph 0024: “The wireless unit 30 has a function of reading out biometric information from the memory unit 20 and wirelessly transmitting it, and a wireless module 31 is provided as a main circuit unit. The wireless module 31 is a circuit unit that intermittently performs wireless communication using a general-purpose wireless communication method such as Bluetooth or Zigbee, and a wireless control unit 32 is provided as a main processing unit.”, Paragraph 0025: “The wireless control unit 32 includes a control circuit such as a microcomputer, and includes a control circuit such as a microcomputer that executes information processing by executing a program.”, “wirelessly transmitting them to the external device 50”), and
However, Okabe does not teach
a memory connected to the second processor and inaccessible from the first processor,
wherein the first processor
specifies an address of a write destination in the memory and causes the second processor to write the biological data into the memory, and
specifies an address of a read source in the memory and causes the second processor to read the biological data from the memory and transmit the biological data to the information terminal.
Kwon teaches a memory (Flash memory 300) connected to the second processor (second processor 200) and inaccessible from the first processor (first processor 100) (Paragraph 0025: “Flash memory 300 is coupled to second processor 200.”, and Fig3 illustrates first processor and second processor connected to a flash memory connected directly to the second processor, Paragraph 0025: “First processor 100 communicates with second processor 200 via DRAM 400 without the use of external interfacing, thereby indirectly accessing flash memory 300. In this manner, when first processor 100 is coupled to DRAM 400, first processor 100 indirectly accesses flash memory 300 which is connected to second processor 200. “, and Paragraph 0029: “This control command allows first processor 100 to indirectly access flash memory 300 by utilizing the shared memory area 11 and internal register 50. This is done even when only second processor 200 is coupled to flash memory 300”, and the Examiner notes that inaccessible, as best understood in light of the specification, means no direct access),
wherein the first processor (first processor 100)
specifies an address of a write destination in the memory (physical address in flash memory 300) (Paragraph 0042: “first processor 100 searches for a physical address corresponding to a logical address”, “first processor 100 writes, physical address of flash memory, write data size, address of shared memory area 11 (where write data is stored), and the write command in first mailbox area 52”, Paragraph 0044: “first processor 100 only handles the logical address of flash memory in the write operation, step S11 is skipped and the logical address of the flash memory is written in first mailbox area 52 in step S12. Second processor 200 searches for the physical address corresponding to the logical address based on the information from storage table area 110. Second processor 200 directly searches for an address map table allocated to the interior of flash memory 300.”, and Paragraph 0045: “first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52.”) and
causes the second processor (second processor 200) to write the biological data into the memory (Paragraph 0042: “first processor 100 transmits an interrupt signal INTb.”, Paragraph 0043: “the data written to shared memory area 11 is read and the data is written to a corresponding physical address of the flash memory 300 based on the contents of data read from first mailbox area 52”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100 based on the contents read from first mailbox area 52”), and
specifies an address of a read source in the memory (physical address in flash memory 300) (Paragraph 0045: “first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52.”) and
causes the second processor (second processor 200) to read the biological data from the memory (Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100 based on the contents read from first mailbox area 52”) and
Kudo teaches the first processor (CTLa MTU 101a) causes the second processor (CTLb MTU 101b) to transmit the data to the information terminal (Paragraph 0042: “The CTLa comprises an MPU 101a, an MPU memory 102a, a DMA 103a, a HOST_I/F (I/F: abbreviation for interface, the same subsequently) 104a, a DRIVE_I/F 105a, and a management_I/F 106a. The same is true of the CTLb. The HOST_I/F 104a of the CTLa and the HOST_I/F 104b of the CTLb are each connected to the host 2 via the SAN 5.”, Paragraph 0059: “The request transmission program 207 a issues a request to or via the MPU 101 b of the external system controller 101 a for access to enable the configuration management program 201 a or basic I/O program 202 a to read or write to the SM12 b and the cache memory 13 b of the MPU memory 102 b of the external system controller 100 b and to start up the interfaces 104 b and 105 b and the DMA 103 b”, Paragraph 0109: “the basic I/O program starts the request transmission program 207 a in order to request the startup of the HOST_IF access program 210 b of the external system controller 100 b”, Paragraph 0113: “Upon receiving a response from the HOST_IF access program 210 a of the internal system controller 100 a which is the startup target in S1013 or receiving a response from the HOST_IF access program 210 b of the external system controller 100 b which is the startup target in S1014”, and Fig. 1) (the examiner note: Okabe teaches the data comprises the biological data above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe’s control method with Kwon to incorporate indirect memory-access arrangement, in which the first processor specifies read/write addresses and the second processor performs the corresponding memory operations with biological data because incorporating such an arrangement would have allowed multiple processors to use a single flash memory while reducing memory cost and system size (Kown, Abstract; Paragraph 0025,0029,0036)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe in view of Kwon by incorporating request-controlled interface arrangement, as taught by Kudo, because incorporating such an arrangement would have allowed the first processor to initiate data transmission through an interface controlled by the second processor (Kudo, Paragraph 0059,0109,0113). When applied to Okabe, the transmitted data would be Okabe’s biological data, and the interface would be the wireless interface of wireless control unit 32 communicating with external device 50 (Okabe, Paragraph 0024-0025, 0030).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Okabe in view of Kwon, Kudo and further in view of “Kubo” (US20200145832A1).
Regarding claim 4, Okabe in view of Kwon and Kudo teaches the measurement device of claim 3 (see rejection claim 3 above).
Okabe does not teach wherein the first processor outputs a blood pressure measurement result based on the pulse wave data.
Kubo teaches wherein the first processor outputs a blood pressure measurement result based on the pulse wave data (Paragraph 0111: “the controller 111 interprets and executes, courtesy of the CPU, the program to control each hardware element shown in FIG. 4. Thus, as shown in FIG. 11, the sensor device 100 functions as a computer having a biological sensor 101, a motion sensor 102, a clock unit 103, an input unit 104, a data management unit 105, a data storage unit 106, a transmission control unit 107, a transmission unit 108, a display control unit 109, and a display unit 110”, Paragraph 0112: “The biological sensor 101 typically includes a blood pressure monitor that obtains blood pressure data by measuring a blood pressure of the user”, Paragraph 0128: “The display control unit 109 receives the date and time data and the sensor data from the data management unit 105, and generates the display data from the display unit 110 based on the data.”, “The display control unit 109 transmits the generated display data to the display unit 110. “, and Paragraph 130: “The display unit 110 receives the display data from the display control unit 109 and displays the display data.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okabe in view of Kwon by incorporating Kubo’s pulse-wave-based blood-pressure measurement and output arrangement, in which a processor-controlled sensor device obtains continuous blood-pressure measurements from pulse transit time and outputs the resulting sensor data through a display, because such an arrangement would have allowed pulse-wave information to be used to obtain beat-by-beat blood-pressure values and present the measurement results to the user (Kubo, Paragraph 0111-0113,0128-0130).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kudo in view of Okabe and Kwon.
Regarding claim 7.
Kudo teaches A control recording medium of (Basic I/O program 202a and/or request-transmission program 207a in MPU memory 102a) (Paragraph 0044: “The configuration of the MPU memory 102a of the CTLa will be described next on the basis of FIG. 2. .The MPU memory 102b of the CTLb is the same. The MPU 102a comprises a text area 10a, an area for a local memory 11a, an area for a communication area 14a, an area of a shared memory (called "SM" hereinbelow) 12a, an area of a cache memory 13a, each area is configured as an address area. The areas each store programs, control information, or various data.”, Paragraph 0045: “The text area 10a stores various programs enabling the storage system to implement its functions.”, “The software resources comprise a configuration management program 201, a basic I/O program 202, a timer synchronization program 203a, a proxy access program 204a, an interrupt reception program 205a, a normal reception program 206a, a request transmission program 207a, an SM access program 208a, a DMA access program 209a, a HOST_IF access program 210a, and a DRIVE_IF access program 211a. These programs are executed by the MPU 101a.”, Paragraph 0056: “Upon executing a read I/O or write I/O, the basic I/O program 202a calls, as necessary, the request transmission program 207a, the SM access program 208a, the DMA access program 209a, the HOST_IF access program 210a, and the DRIVE_IF access program 211a, and the like, and executes each program.”, and Paragraph 0059: “The request transmission program 207a issues a request to or via the MPU 101b of the external system controller 101a for access to enable the configuration management program 201a or basic I/O program 202a to read or write to the SM12b and the cache memory 13b of the MPU memory 102b of the external system controller 100b”).
the control recording medium (Basic I/O program 202a and/or request-transmission program 207a in MPU memory 102a) for causing the first processor (MTU 101a) to execute processing of (Paragraph 0042: “The CTLa comprises an MPU 101a, an MPU memory 102a, a DMA 103a, a HOST_I/F (I/F: abbreviation for interface, the same subsequently) 104a, a DRIVE_I/F 105a, and a management_I/F 106a. The same is true of the CTLb. The HOST_I/F 104a of the CTLa and the HOST_I/F 104b of the CTLb are each connected to the host 2 via the SAN 5.”, Paragraph 0044: “The configuration of the MPU memory 102a of the CTLa will be described next on the basis of FIG. 2. The MPU memory 102b of the CTLb is the same. The MPU 102a comprises a text area 10a, an area for a local memory 11a, an area for a communication area 14a, an area of a shared memory (called "SM" hereinbelow) 12a, an area of a cache memory 13a, each area is configured as an address area. The areas each store programs, control information, or various data.”, Paragraph 0045: “The text area 10a stores various programs enabling the storage system to implement its functions.”, and Paragraph 0052: “The software resources comprise a configuration management program 201, a basic I/O program 202, a timer synchronization program 203a, a proxy access program 204a, an interrupt reception program 205a, a normal reception program 206a, a request transmission program 207a, an SM access program 208a, a DMA access program 209a, a HOST_IF access program 210a, and a DRIVE_IF access program 211a. These programs are executed by the MPU 101a.”, Paragraph 0056: “Upon executing a read I/O or write I/O, the basic I/O program 202a calls, as necessary, the request transmission program 207a, the SM access program 208a, the DMA access program 209a, the HOST_IF access program 210a, and the DRIVE_IF access program 211a, and the like, and executes each program.”, and Paragraph 0059: “The request transmission program 207a issues a request to or via the MPU 101b of the external system controller 101a for access to enable the configuration management program 201a or basic I/O program 202a to read or write to the SM12b and the cache memory 13b of the MPU memory 102b of the external system controller 100b”).
causing the first processor (MTU 101a) to execute processing of causing the second processor (MTU 101b) to transmit the data to the information terminal (Host 2) (Paragraph 0042: “The CTLa comprises an MPU 101a, an MPU memory 102a, a DMA 103a, a HOST_I/F (I/F: abbreviation for interface, the same subsequently) 104a, a DRIVE_I/F 105a, and a management_I/F 106a. The same is true of the CTLb. The HOST_I/F 104a of the CTLa and the HOST_I/F 104b of the CTLb are each connected to the host 2 via the SAN 5.”, Paragraph 0059: “The request transmission program 207 a issues a request to or via the MPU 101 b of the external system controller 101 a for access to enable the configuration management program 201 a or basic I/O program 202 a to read or write to the SM12 b and the cache memory 13 b of the MPU memory 102 b of the external system controller 100 b and to start up the interfaces 104 b and 105 b and the DMA 103 b”, Paragraph 0109: “the basic I/O program starts the request transmission program 207 a in order to request the startup of the HOST_IF access program 210 b of the external system controller 100 b”, Paragraph 0113: “Upon receiving a response from the HOST_IF access program 210 a of the internal system controller 100 a which is the startup target in S1013 or receiving a response from the HOST_IF access program 210 b of the external system controller 100 b which is the startup target in S1014”, and Fig. 1) (the examiner note: Okabe teaches that the data comprises the biological data below).
However, Kudo does not teach a measurement device including a first processor that performs measurement based on biological data obtained by a sensor, a second processor that performs wireless communication with an information terminal, and a memory connected to the second processor and inaccessible from the first processor,
specifying an address of a write destination in the memory and causing the second processor to write the biological data into the memory, and
specifying an address of a read source in the memory and causing the second processor to read the biological data from the memory.
Okabe teaches a measurement device (Paragraph 0020, 0022) including a first processor (sensor control unit 13) that performs measurement based on biological data obtained by a sensor (Paragraph 0021: “The sensor element 11 is an element that measures biological information from a living body test part. Here, the sensor element 11 includes a light emitting element and a light receiving element.”, and Paragraph 0022: ”The sensor control unit 13 includes a control circuit such as a microcomputer that executes information processing by executing a program”),
a second processor (wireless control unit 32) that performs wireless communication with an information terminal (external device 50) (Paragraph 0024: “The wireless unit 30 has a function of reading out biometric information from the memory unit 20 and wirelessly transmitting it, and a wireless module 31 is provided as a main circuit unit. The wireless module 31 is a circuit unit that intermittently performs wireless communication using a general-purpose wireless communication method such as Bluetooth or Zigbee, and a wireless control unit 32 is provided as a main processing unit”, Paragraph 0025: “The wireless control unit 32 includes a control circuit such as a microcomputer, and includes a control circuit such as a microcomputer that executes information processing by executing a program.”, “wirelessly transmitting them to the external device 50”), and
Kwon teaches a memory (flash memory 300) connected to the second processor (second processor 200) (Paragraph 0025: “Flash memory 300 is coupled to second processor 200.”, and Fig. 3 illustrates first processor and second processor connected to a flash memory dedicated to the second processor) and
inaccessible from the first processor (first processor 100) (Paragraph 0025: “First processor 100 communicates with second processor 200 via DRAM 400 without the use of external interfacing, thereby indirectly accessing flash memory 300. In this manner, when first processor 100 is coupled to DRAM 400, first processor 100 indirectly accesses flash memory 300 which is connected to second processor 200.”, and Paragraph 0029: “This control command allows first processor 100 to indirectly access flash memory 300 by utilizing the shared memory area 11 and internal register 50. This is done even when only second processor 200 is coupled to flash memory 300”, and the Examiner notes that inaccessible, as best understood in light of the specification, means no direct access),
the first processor (first processor 100) to execute processing of specifying an address of a write destination in the memory (Flash memory 300) (Paragraph 0042: “first processor 100 searches for a physical address corresponding to a logical address”, “first processor 100 writes, physical address of flash memory, write data size, address of shared memory area 11 (where write data is stored), and the write command in first mailbox area 52”, Paragraph 044: “first processor 100 only handles the logical address of flash memory in the write operation, step S11 is skipped and the logical address of the flash memory is written in first mailbox area 52 in step S12. Second processor 200 searches for the physical address corresponding to the logical address based on the information from storage table area 110. Second processor 200 directly searches for an address map table allocated to the interior of flash memory 300.”, and Paragraph 0045: “first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52.”) and
causing the second processor (second processor 200) to write the biological data into the memory (flash memory 300) (Paragraph 0042: “first processor 100 transmits an interrupt signal INTb.”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100 based on the contents read from first mailbox area 52”), and
specifying an address of a read source in the memory (flash memory 300) (Paragraph 0045: “first processor 100 searches for the physical address corresponding to the logical address referring to storage table area 110 of shared memory area 11. In step S22, first processor 100 writes a physical address of the flash memory, the physical address of the flash memory, the read data size, an address of the shared memory area 11 (into which read data will be stored), and a read command in first mailbox area 52”) and
causing the second processor (second processor 200) to read the biological data from the memory (flash memory 300) (Paragraph 0045: “First processor 100 transmits an interrupt signal INTb in step S23.”, and Paragraph 0046: “second processor 200 accesses flash memory 300 and reads data stored with the corresponding physical address designated by first processor 100”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudo with Okabe because incorporating Okabe’s biological-information measurement and wireless transmission functions into Kudo’s program-controlled dual-processor system would have enabled the measured biological data to be processed and continuously transmitted wirelessly to an external information terminal (Kudo, Paragraphs 0052, 0059-0060, 0073,0078; Okabe, Paragraphs 0008, 0011-0014,0020-0025)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudo with Kwon because incorporating Kown’s memory arrangement into Kudo’s dual-processor system would have allowed the first processor to initiate addressed memory operations while the second processor directly accesses the memory, thereby reducing duplicate memory, system size, and cost (Kudo, Paragraph 0059,0109,0113; Kwon, Paragraphs 0007-0010,0025,0029,0036).
Conclusion
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/MORGAN SANGJO SHIM/Examiner, Art Unit 3791
/PATRICK FERNANDES/Primary Examiner, Art Unit 3791
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