DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is responsive to amendment filed on 02/02/26.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Orio (Orio et al. US 2020/0111423) in view of Han et al. (US 2021/0074201).
Regarding claim 1, Orio discloses a display device (100, fig. 1, paras. 0019-
0020), comprising:
a display panel (10) including a plurality of pixels (6); and
a luminance compensating unit (27, paras. 0032-0035) configured to adjust a
gamma voltage (15) according to a difference value between a first high potential voltage (ELVDD at 31) and a second high potential voltage (ELVDD at 32), the first high potential voltage being supplied to a pixel that is most adjacent to one side of the display panel, among the plurality of pixels, and the second high potential voltage being
supplied to a pixel that is most adjacent to another side of the display panel, among the
plurality of pixels (paras. 0041-0043).
Orio does not specifically disclose wherein the luminance compensating unit is configured to receive the first high potential voltage from the pixel most adjacent to one side of the display panel, and to receive the second high potential voltage from the pixel most adjacent to the other side of the display panel.
In a similar field of endeavor of display device, Han disclose a luminance compensating unit (such as voltage compensation circuit, para. 0044) is configured to receive the first high potential voltage (such as first input signal provides a pixel voltage of pixel A, fig. 1, paras. 0040, 0056 and 0066) from the pixel (A) most adjacent to one side of the display panel, and to receive the second high potential voltage (such as second input signal provides a pixel voltage of pixel B, fig. 1, paras. 0040, 0056 and 0066) from the pixel most adjacent to the other side of the display panel.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filling date of the claimed invention to incorporate the compensation circuit as taught by Han in the system of Orio in order to reduce the horizonal crosstalk of the display panel (para. 0065).
Regarding claim 2, Orio discloses the luminance compensating unit includes:
a source high potential voltage compensating unit (26, 27, paras. paras. 0041- 0043) configured to output a source high potential voltage compensated according to
the difference value between the first high potential voltage and the second high
potential voltage; and
a gamma voltage generating unit (28, paras. paras. 0041-0043) configured to
output a gamma voltage according to the compensated source high potential voltage.
Regarding claims 8 and 13, Orio discloses a first sensing line connected to the
pixel that is most adjacent to the one side of the display panel, and configured to
transmit a supplied first high potential voltage to the luminance compensating unit
(paras. 0041-0042); and
a second sensing line connected to the pixel that is most adjacent to the another
side of the display panel, and configured to transmit a supplied second high potential
voltage to the luminance compensating unit (paras. 0041-0042).
Regarding claim 9, Orio discloses a display device (100, fig. 1, paras. 0019-
0020), comprising:
a display panel (10) including a plurality of pixels (6);
a data driver (20) configured to supply a data voltage to the plurality of pixels
through a plurality of data lines, according to a gamma voltage; and
a luminance compensating unit (27, paras. 0032-0035) configured to adjust the
gamma voltage (15) according to a difference value between a first high potential
voltage (ELVDD at 31) and a second high potential voltage( ELVDD at 32), the first high
potential voltage being supplied to a pixel disposed in a first pixel line, among the
plurality of pixels, and the second high potential voltage being supplied to a pixel
disposed in a last pixel line, among the plurality of pixels (paras. 0041-0043).
Orio does not specifically disclose wherein the luminance compensating unit is configured to receive the first high potential voltage from the pixel most adjacent to one side of the display panel, and to receive the second high potential voltage from the pixel most adjacent to the other side of the display panel.
In a similar field of endeavor of display device, Han disclose a luminance compensating unit (such as voltage compensation circuit, para. 0044) is configured to receive the first high potential voltage (such as first input signal provides a pixel voltage of pixel A, fig. 1, paras. 0040, 0056 and 0066) from the pixel (A) most adjacent to one side of the display panel, and to receive the second high potential voltage (such as second input signal provides a pixel voltage of pixel B, fig. 1, paras. 0040, 0056 and 0066) from the pixel most adjacent to the other side of the display panel.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filling date of the claimed invention to incorporate the compensation circuit as taught by Han in the system of Orio in order to reduce the horizonal crosstalk of the display panel (para. 0065).
Claims 3-6 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Orio in view of Han and further in view of Kim (Kim et al. US 2020/0211457).
Regarding claim 3, the combination of Orio and Han does not specifically disclose "the source high potential voltage compensating unit…the source high potential voltage".
In a similar field of endeavor of a display device, Kim discloses a source high
potential voltage compensating unit (fig. 11, paras. 0111-0113) includes:
a voltage drop amount amplifying unit (10) configured to amplify and output the
difference value between the first high potential voltage (ELVDD) and the second high
potential voltage (INT_ELVDD); and
a source high potential voltage amplifying unit (20) configured to output the
source high potential voltage (INT_VH) compensated by adding the amplified difference
value (V0) and the source high potential voltage (INT_VH).
Therefore, it would have been obvious to one of ordinary skill in the art before
effective filling date of the claimed invention to incorporate the compensating unit as
taught by Kim in the system of Orio and Han in order to prevent the luminance of the screen from varying with the voltage drop in display panel.
Regarding claim 4, the combination of Orio, Han and Kim discloses the voltage drop amount amplifying unit (10, fig. 11, paras. 0111-0113 of Kim) includes:
an inverting input terminal (ELVDD terminal);
a non-inverting input terminal (INT_ELVDD terminal);
an output terminal (VO terminal);
a first resistor (R1) connected to the inverting input terminal;
a second resistor (R2) and a third resistor (R3) connected to the non-inverting
input terminal; and
a first feedback resistor (Rf) connected between the output terminal and the
inverting input terminal.
Regarding claim 5, the combination of Orio, Han and Kim discloses the source high potential voltage amplifying unit (20, fig. 11, paras. 0111-0113 of Kim) includes:
an inverting input terminal (R1' terminal);
a non-inverting input terminal (R2' terminal);
an output terminal (VH terminal);
a fourth resistor (R3') connected to the input terminal;
a fifth resistor (R1') connected between an output terminal (V0 terminal) of the
voltage drop amount amplifying unit and the input terminal;
a sixth resistor (R2') connected between the non-inverting input terminal and a
line to which the source high potential voltage is supplied; and
a second feedback resistor (Rf) connected between the output terminal of the
source high potential voltage amplifying unit and the inverting input terminal. Although
Kim does not specifically disclose the fourth resistor connected to the inverting input terminal and the fifth resistor connected to non-inverting input terminal. However, it
would have been obvious to obtain these connections to receive the same output
voltage.
Regarding claims 6 and 11, the combination of Orio, Han and Kim discloses the
difference value output (V0) from the voltage drop amount amplifying unit (10) is input to
a non-inverting input terminal (+) of the source high potential voltage amplifying unit
(20), and the source high potential voltage (INT_VH) is input to the non- inverting input
terminal (+) of the source high potential voltage amplifying unit (20) (fig. 11, paras.
0111-0113 of Kim).
Regarding claim 10, the combination of Orio, Han and Kim discloses the luminance compensating unit includes:
a first amplifying unit (10, fig. 11, paras. 0111-0113 of Kim) configured to amplify
and output the difference value between the first high potential voltage and the second
high potential voltage;
a second amplifying unit (20, fig. 11, paras. 0111-0113 of Kim) configured to
output a compensated source high potential voltage obtained by adding the difference
value and a source high potential voltage; and
a gamma voltage generating unit (112, fig. 1, para. 0041 of Kim) configured to
supply a gamma voltage to the data driver according to the compensated source high
potential voltage.
Claims 7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Orio in view of Han and further in view of Bae (Bae et al. US 2018/0211579).
Regarding claims 7 and 12, the combination of Orio and Han does not specifically disclose "the gamma voltage generating unit…source high potential voltage".
In a similar field of endeavor of display device, Bae discloses the gamma voltage generating unit (208, fig. 3) includes:
a first gamma voltage generating unit (208a_1, para. 0076) configured to output
a gamma voltage of a red sub pixel according to the compensated source high potential
voltage; and
a second gamma voltage generating unit (208a_2, para. 0078) configured to
output gamma voltages of a green sub pixel and a blue sub pixel according to the
compensated source high potential voltage.
Therefore, it would have been obvious to one of ordinary skill in the art before
effective filling date of the claimed invention to incorporate the first and the second voltage generating units as taught by Bae in the system of Orio and Han in order to allow the brightness of the display panel might be more easily controlled.
Response to Arguments
Applicant’s arguments with respect to claims 1-13 have been considered but are moot because the new ground of rejection does not rely on at least one reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER T NGUYEN whose telephone number is (571)272-7696. The examiner can normally be reached Mon-Fri 7:00-5:00.
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/JENNIFER T NGUYEN/Primary Examiner, Art Unit 2629