Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 21-40 are pending. Claims 1-20 are cancelled.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12,265,438 B2 (“the ’438 patent”). The ’438 patent names the same inventors, is commonly assigned to Apple Inc., shares an identical specification, and is the parent of the present continuation. Although the conflicting claims are not identical, they are not patentably distinct, as explained below.
Independent claim 21 (and, mutatis mutandis, claims 30 and 40) is not patentably distinct from the granted claims because it recites the combination of (a) granted independent claim 1, as claimed, an IC/SOC having an interface circuit with a plurality of devices that individually interface the IC to external ICs via respective serial communication links, and a bridge circuit that causes a subset of the devices to transition from a regular (higher-power) state to a low-power state furthermore and (b) granted dependent claim 2, as claimed, the address-hazard gate in which the bridge determines whether a first packet to be transferred is directed to the same address range as a second packet already transferred through the subset, routes the first packet through the same subset, and only then transitions the subset. A claim reciting the combination of an issued independent claim and its issued dependent claim is not patentably distinct from those issued claims; the difference in wording (“IC” vs. “SOC,” “first/second power state” vs. “regular/low power state”) is immaterial. The pending dependent claims correspond element-for-element to dependent claims of the ’438 patent, as mapped below.
Present Application
Pat No. 12,265,348
21. A integrated circuit (IC), comprising: an interface circuit comprising a plurality of devices individually interfacing the IC via respective serial communication links to one or more external ICs, wherein the devices are configured to individually transition between a first power state and a second power state; and a bridge circuit controlling the interface circuit, the bridge circuit configured to cause a subset of devices of the plurality of devices to transition from the first power state to the second power state, wherein to cause the subset of devices to transition, the bridge circuit is configured to: determine that a packet to be transferred to one of the plurality of devices is directed to a same address range as a previous packet transferred to one of the subset of devices, and responsive to the determining: cause the packet to be transferred to the one of the subset of devices; and cause transition of the subset of devices from the first power state to the second power state.
22. The IC of claim 21, wherein the address range corresponds to a cache line of an external memory device.
23. The IC of claim 21, wherein the bridge circuit is further configured to: obtain an additional indication to cause the subset of devices of the interface circuit to transition from the second power state to the first power state; determine that another packet to be transferred to the subset of devices is directed to another same address range as another previously transferred packet, and responsive to the determining: cause the other packet to be transferred to the subset of devices for transmission to the one or more external ICs; and cause transition of the subset of devices from the second power state to the first power state responsive to determining that transmission of the other packet to the one or more external ICs is complete.
24. The IC of claim 21, wherein the packets transferred by the interface circuit between the IC and external ICs include packets from or to heterogenous networks of the IC.
25. The IC of claim 24, wherein the interface circuit is configured to preserve different communication requirements associated with heterogenous networks of the IC such that transition of the subset of devices from the first power state to the second power state is transparent to the heterogenous networks of the IC.
24. The IC of claim 21, wherein the first power state is a high power state, wherein the second power state is a low power state, wherein the interface circuit comprises a plurality of power control circuits for respective ones of the plurality of devices, and wherein to transition the subset of devices to the second power state, the interface circuit is configured to decrease a clock frequency of the subset of devices and/or decrease a supply voltage of the subset of devices using a subset of the plurality of power control circuits corresponding to the subset of devices.
25. The IC of claim 21, wherein to transition the subset of devices to the second power state, the interface circuit is configured to reduce a data rate used by the subset of devices to transfer packets.
26. The IC of claim 21, wherein to transition the subset of devices to the second power state, the interface circuit is configured to turn off the subset of devices.
27. The IC of claim 21, wherein the subset of devices comprises at least one of a transmitter, a receiver, or a transceiver.
28. The IC of claim 27, wherein the transmitter comprises a serializer, wherein the receiver comprises a deserializer, and wherein the transceiver comprises a serializer and a deserializer.
29. The IC of claim 21, further comprising: a plurality of processors; a plurality of memory controllers configured to control access to memory devices; and a plurality of peripheral devices.
30. A system, comprising: a plurality of integrated circuits (ICs) individually implemented on respective semiconductor dies that are coupled with one another via one or more serial communication links, wherein an individual one of the ICs comprises: an interface circuit comprising a plurality of devices individually interfacing the IC via respective serial communication links to one or more external ICs, wherein the devices are configured to individually transition between a first power state and a second power state; and a bridge circuit controlling the interface circuit, the bridge circuit configured to cause a subset of devices of the plurality of devices to transition from the first power state to the second power state, wherein to cause the subset of devices to transition, the bridge circuit is configured to: determine that a packet to be transferred to one of the plurality of devices is directed to a same address range as a previous packet transferred to one of the subset of devices, and responsive to the determining: cause the packet to be transferred to the one of the subset of devices; and cause transition of the subset of devices from the first power state to the second power state.
31. The system of claim 30, wherein the address range corresponds to a cache line of an external memory device.
32. The system of claim 30, wherein the bridge circuit is further configured to: obtain an additional indication to cause the subset of devices of the interface circuit to transition from the second power state to the first power state; determine that another packet to be transferred to the subset of devices is directed to another same address range as another previously transferred packet, and responsive to the determining: cause the other packet to be transferred to the subset of devices for transmission to the one or more external ICs; and cause transition of the subset of devices from the second power state to the first power state responsive to determining that transmission of the other packet to the one or more external ICs is complete.
33. The system of claim 30, wherein the packets transferred by the interface circuit between the IC and external ICs include packets from or to heterogenous networks of the IC.
34. The system of claim 33, wherein the interface circuit is configured to preserve different communication requirements associated with heterogenous networks of the IC such that transition of the subset of devices from the first power state to the second power state is transparent to the heterogenous networks of the IC.
35. The system of claim 30, wherein the first power state is a high power state, wherein the second power state is a low power state, wherein the interface circuit comprises a plurality of power control circuits for respective ones of the plurality of devices, and wherein to transition the subset of devices to the second power state, the interface circuit is configured to decrease a clock frequency of the subset of devices and/or decrease a supply voltage of the subset of devices using a subset of the plurality of power control circuits corresponding to the subset of devices.
36. The system of claim 30, wherein to transition the subset of devices to the second power state, the interface circuit is configured to reduce a data rate used by the subset of devices to transfer packets.
37. The system of claim 30, wherein to transition the subset of devices to the second power state, the interface circuit is configured to turn off the subset of devices.
38. The system of claim 30, wherein the subset of devices comprises at least one of a transmitter, a receiver, or a transceiver.
39. The system of claim 38, wherein the transmitter comprises a serializer, wherein the receiver comprises a deserializer, and wherein the transceiver comprises a serializer and a deserializer.
40. A method, comprising: causing, by a bridge circuit of an integrated circuit (IC), a subset of devices of a plurality of devices, individually interfacing the IC via respective serial communication links to one or more external ICs, to transition from the first power state to the second power state, comprising: determining that a packet to be transferred to one of the plurality of devices is directed to a same address range as a previous packet transferred to one of the subset of devices, and responsive to the determining: causing the packet to be transferred to the one of the subset of devices; and causing transition of the subset of devices from the first power state to the second power state.
1. A system on a chip (SOC), comprising: an interface circuit comprising a plurality of devices configured to transfer packets between the SOC and one or more other SOCs external to the SOC, wherein the SOC and external SOCs are individually implemented on respective semiconductor dies, wherein the semiconductor die of the SOC is coupled with the semiconductor dies of the external SOCs via one or more serial communication links, and wherein the plurality of devices is configured to interface the SOC with the serial communication links; and a bridge circuit configured to control the interface circuit, wherein the bridge circuit is configured to: obtain an indication to cause a subset of the devices to transition from a regular state to a low power state; and generate at least one signal for the subset of devices in response to the indication, and wherein the interface circuit is configured to: obtain the signal generated from the bridge circuit; and transition the subset of devices from the regular state to the low power state according to the signal from the bridge circuit, and maintain another subset of the devices in the regular state.
2. The SOC of claim 1, wherein to generate the at least one signal, the bridge circuit is configured to: determine whether a first packet to be transferred is directed to an address range same as a second packet that has been transferred through the subset of devices; in response to a determination that the first packet to be transferred is directed to the address range same as the second packet that has been transferred, cause the first packet to be routed to the same subset of devices that was used to transfer the second packet; determine whether the first packet has been transferred through the subset of devices; and in response to a determination that the first packet is transferred through the subset of devices, generate the at least one signal to transition the subset of devices to the low power state.
12. The SOC of claim 2, wherein the address range corresponds to a cache line of an external memory device.
3. The SOC of claim 1, wherein the bridge circuit is further configured to: obtain an additional indication to cause the subset of devices of the interface circuit to transition out of the low power state; determine whether a first packet to be transferred is directed to an address range same as a second packet that has been transferred through the subset of devices during the low power state; in response to a determination that the first packet to be transferred is directed to the address range same as the second packet that has been transferred, cause the first packet to be routed to the same subset of devices that was used to transfer the second packet during the low power state; determine whether the first packet has been transferred through the subset of devices; and in response to a determination that the first packet is transferred through the subset of devices, generate at least one additional signal for the subset of devices, and wherein the interface circuit is further configured to: obtain the at least one additional signal generated from the bridge circuit; and transition the subset of devices out of the low power state according to the additional signal from the bridge circuit.
4. The SOC of claim 1, wherein the packets transferred by the interface circuit between the SOC and external SOCs include packets from or to heterogenous networks of the SOC.
5. The SOC of claim 1, wherein the interface circuit is configured to preserve different communication requirements associated with heterogenous networks of the SOC, such that transition of the subset of devices from the regular state to the low power state is transparent to the heterogenous networks of the SOC.
6. The SOC of claim 1, wherein the interface circuit comprises a plurality of power control circuits for respective ones of the plurality of devices, and wherein to transition the subset of devices to the low power state, the interface circuit is configured to (a) decrease a clock frequency of the subset of devices, (b) decrease a supply voltage of the subset of devices, (c) or a combination therefore, using a subset of the plurality of power control circuits corresponding to the subset of devices.
7. The SOC of claim 1, wherein to transition the subset of devices to the low power state, the interface circuit is configured to reduce a data rate used by the subset of devices to transfer packets.
8. The SOC of claim 1, wherein to transition the subset of devices to the low power state, the interface circuit is configured to turn off the subset of devices.
9. The SOC of claim 1, wherein the subset of devices comprises at least one of: a transmitter, a receiver, or a transceiver.
13. The SOC of claim 9, wherein the transmitter comprises a serializer, wherein the receiver comprises a deserializer, and wherein the transceiver comprises a serializer and a deserializer.
11. The SOC of claim 1, further comprising: a plurality of processors; a plurality of memory controllers configured to control access to memory devices; and a plurality of peripheral devices.
14. A system, comprising: a plurality of systems on a chip (SOCs), wherein the SOCs are individually implemented on respective semiconductor dies that are coupled with each other via one or more serial communication links, and wherein an individual one of the SOCs comprises: an interface circuit configured to interface the individual SOC with the serial communication links, wherein the interface circuit comprises a plurality of devices configured to transfer packets (a) from the individual SOC to other SOCs or (b) from the other SOCs to the individual SOC; and a bridge circuit configured to control the interface circuit, wherein the bridge circuit is configured to: obtain an indication to cause a subset of the devices to transition from a regular state to a low power state; and generate at least one signal for the subset of devices in response to the indication, and wherein the interface circuit is configured to: obtain the signal generated from the bridge circuit; and transition the subset of devices from the regular state to the low power state according to the signal from the bridge circuit, and maintain another subset of the devices in the regular state.
15. The system of claim 14, wherein to generate the at least one signal, the bridge circuit is configured to: determine whether a first packet to be transferred is directed to an address range same as a second packet that has been transferred through the subset of devices; in response to a determination that the first packet to be transferred is directed to the address range same as the second packet that has been transferred, cause the first packet to be routed to the same subset of devices that was used to transfer the second packet; determine whether the first packet has been transferred through the subset of devices; and in response to a determination that the first packet is transferred through the subset of devices, generate the at least one signal to transition the subset of devices to the low power state.
12. The SOC of claim 2, wherein the address range corresponds to a cache line of an external memory device.
15. The system of claim 14, wherein to generate the at least one signal, the bridge circuit is configured to: determine whether a first packet to be transferred is directed to an address range same as a second packet that has been transferred through the subset of devices; in response to a determination that the first packet to be transferred is directed to the address range same as the second packet that has been transferred, cause the first packet to be routed to the same subset of devices that was used to transfer the second packet; determine whether the first packet has been transferred through the subset of devices; and in response to a determination that the first packet is transferred through the subset of devices, generate the at least one signal to transition the subset of devices to the low power state.
4. The SOC of claim 1, wherein the packets transferred by the interface circuit between the SOC and external SOCs include packets from or to heterogenous networks of the SOC.
5. The SOC of claim 1, wherein the interface circuit is configured to preserve different communication requirements associated with heterogenous networks of the SOC, such that transition of the subset of devices from the regular state to the low power state is transparent to the heterogenous networks of the SOC.
6. The SOC of claim 1, wherein the interface circuit comprises a plurality of power control circuits for respective ones of the plurality of devices, and wherein to transition the subset of devices to the low power state, the interface circuit is configured to (a) decrease a clock frequency of the subset of devices, (b) decrease a supply voltage of the subset of devices, (c) or a combination therefore, using a subset of the plurality of power control circuits corresponding to the subset of devices.
17. The system of claim 14, wherein to transition the subset of devices to the low power state, the interface circuit is configured to (a) reduce a data rate used by the subset of devices to transfer packets, or (b) turn off the subset of devices.
17. The system of claim 14, wherein to transition the subset of devices to the low power state, the interface circuit is configured to (a) reduce a data rate used by the subset of devices to transfer packets, or (b) turn off the subset of devices.
18. The system of claim 14, wherein the subset of devices comprises at least one of: a serializer transmitter, a deserializer receiver, or a transceiver having a serializer and a deserializer.
18. The system of claim 14, wherein the subset of devices comprises at least one of: a serializer transmitter, a deserializer receiver, or a transceiver having a serializer and a deserializer.
20. A method, comprising: obtaining, by a bridge circuit of a system of a chip (SOC), an indication to cause a subset of a plurality of devices of an interface circuit of the SOC from a regular state to a low power state, wherein the interface circuit transfers packets between the SOC and one or more other SOCs external to the SOC, wherein the SOC and external SOCs are individually implemented on respective semiconductor dies, wherein the semiconductor die of the SOC is coupled with the semiconductor dies of the external SOCs via one or more serial communication links, and wherein the plurality of devices interfaces the SOC with the serial communication links; generating, by the bridge circuit, at least one signal for the subset of devices according to the indication; obtaining, by the interface circuit, the at least one generated signal; and transitioning, by the interface circuit, the subset of devices from the regular state to the low power state according to signal from the bridge circuit, and maintaining another subset of the devices in the regular state.
In re Karlson, 136 USPQ 189 (ccPA 1963).
Claim Interpretation - 35 U.S.C. 112(f)
The “interface circuit” and “bridge circuit” limitations have been considered under 35 U.S.C. 112(f). They are not interpreted under 112(f). The term “circuit” is a structural term that connotes a class of structures to those of ordinary skill, and the specification expressly states that reciting a structure “configured to” perform a function “is expressly intended not to invoke 35 U.S.C. 112(f).” Accordingly, the “… circuit configured to …” limitations are given their ordinary structural meaning and 112(f) is not invoked.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 40 is rejected under 35 U.S.C. 112(b) as indefinite. Claim 40 (an independent method claim) recites causing a subset of devices “to transition from the first power state to the second power state” and later “transition … from the first power state to the second power state,” but the claim does not previously introduce “a first power state” or “a second power state.” There is therefore insufficient antecedent basis for “the first power state” and “the second power state.” For purposes of examination, these are interpreted as a higher-power (regular) state and a lower-power state, respectively. Appropriate correction (e.g., reciting “a first power state and a second power state” when first introduced) is required.
Claim Objections
Claims 21-40 are objected to under 37 CFR 1.126 because the claims, as published, are not numbered consecutively - two claims appear to be numbered “24” and two claims appear to be numbered “25.” Claims must be individually and consecutively numbered in Arabic numerals. Applicant should confirm the intended numbering and renumber the claims consecutively. Any dependency referring to a renumbered claim should be conformed.
Allowable Subject Matter
Claims 21-39 are allowable over the prior of records.
Claim 40 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112, 2nd paragraph, set forth in this Office action.
16. The following is an Examiner's statement of reasons for the indication of allowable subject matter:
The independent claims require, in combination, (i) an integrated circuit / system-on-chip having an interface circuit with a plurality of devices that individually interface the IC to one or more external ICs via respective serial communication links, (ii) a bridge circuit that causes a subset of those devices to transition from a higher- to a lower-power state while another subset is maintained, and (iii) an address-hazard gate determining that a packet to be transferred is directed to the same address range as a previous packet transferred through the subset, routing that packet through the same subset, and only then transitioning the subset. The prior art of record does not teach or reasonably suggest this combination. Notably, the parent patent (US 12,265,438 B2) issued with claims to this subject matter over the same field of art, confirming that the prior art of record does not reach even the base subset-transition limitation, let alone the address-hazard gate. The closest art is summarized below and is made of record.
Brown et al. (US Pat No. 11,216,061) teach the power-domain bridge circuitry that, responsive to a transition indication and to message-identification circuitry detecting a “given message” indicating cessation of communication, initiates a transition to an idle/low-power state (i.e., complete the relevant in-flight communication before powering down). A single power-domain bridge, not a plurality of serial-link devices with a subset placed in low power while another subset is maintained. Gating is by cessation-message detection, not by an address-range match that routes the packet through the same subset.
Peleska et al. (US Pat No. 10,509,762) teach the data rate-adaptive data transfer between a modem and host platform; a low-power mode implemented by reducing the interface data rate. Teaches a low-power state by data-rate reduction (cf. dependent claims), but no subset-of-devices selection and no address-hazard gating.
Georgiou et al. (US Pat No. 7,353,362) teach the multiprocessor SoC with a bridge between a processor-cluster interconnect and the SoC system bus. Teaches an SoC bridge generally, but no subset power-state transition of serial-link interface devices and no address-hazard-gated transition.
The prior art of record does not teach or suggest the claimed combination of a die-to-die interface circuit having a plurality of serial-link devices, a bridge circuit that places a subset of those devices in a low-power state while maintaining another subset, and an address-range hazard gate that routes a same-address packet through the same subset before transitioning. Claims 21-40 would be allowable once (i) the non-statutory double patenting rejection is obviated by a terminal disclaimer over US 12,265,438 B2, (ii) the 35 U.S.C. 112(b) issue in claim 40 is corrected, and (iii) the claims are renumbered consecutively. No prior-art rejection stands against these claims.
Conclusion
All claims are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Gupta et al. (US No. 11,755,489) disclose a configurable interface circuit which is a die-to-die interface architecture.
Gupta et al. (US No. 11,824,795) disclose a communication channels with shared and independent resources which fabric/channel resource management pertinent to subset routing.
Tolchinsky et al. (US No. 12,189,565) disclose a transaction generator for on-chip interconnect fabric which is ordering/transaction handling on the fabric.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
All Internet e-mail communications will be made of record in the application file. PTO employees do not engage in Internet communications where there exists a possibility that sensitive information could be identified or exchanged unless the record includes a properly signed express waiver of the confidentiality requirements of 35 U.S.C. 122. This is more clearly set forth in the Interim Internet Usage Policy published in the Official Gazette of the Patent and Trademark on February 25, 1997 at 1195 OG 89.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see hop://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights