DETAIL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s filing on 02/19/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-2, 4, 6, 11-13, 15, 17 are rejected under 35 U.S.C 103 as being unpatentable over Gong et al. (“Gong”, US Pub 2015/0280584), in view of Arun Khamesra et al. (“Arun”, US Pat 10651753).
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Above annotated Fig. 1a & 4 from Gong et al. (“Gong”, US Pub 2015/0280584)
Regarding independent claim 1, Gong teaches (Fig. 1-4, 6; Para 18-38) a converter (flyback AC-DC converter 10) configured to operate in continuous conduction mode (CCM) (anticipated, but not spelled out explicitly), the converter comprising:
a transformer (106) having a primary winding (108) coupled to a power switch (Power switch 122) and a secondary winding (110) coupled to a synchronous rectifier (SR) field effect transistor (FET) (SR FET 112);
a primary side controller (126) coupled to control the power switch (122); and
a SR controller (140 described as 440) coupled to control the SR FET (SR FET 112), the SR controller (140 described as 440) comprising:
a SR sense pin coupled to a drain of the SR FET (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet);
a gate driver coupled to control a gate of the SR FET (gate driver 442 driving SR FET 112’s gate);
a negative-sensing (NSN) comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38)
coupled between the SR sense pin (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) and the gate driver (gate driver 442 driving SR FET 112’s gate),
wherein the NSN comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34) is operable to generate a turn-on signal based on a voltage on the SR sense pin (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38); and
a detector comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38)
coupled between the SR sense pin (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) and the gate driver (gate driver 442 driving SR FET 112’s gate),
wherein the comparator (404 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34) is operable to generate a first turn-off signal based on the voltage on the SR sense pin (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38);
wherein the gate driver (gate driver 442 driving SR FET 112’s gate) is operable
to turn on the SR FET in response to the turn-on signal from the NSN comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112) and
to turn off the SR FET in response to the first turn-off signal from the comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112);
wherein the SR controller (140 described as 440 operates independent of 126, but does considers output of 108’s, same as Applicants Fig. 4 or 7) is operable to turn off the SR FET (turn off SR FET 112) without turn-on information of the power switch (without turn-on information of power switch 122, in another word during the period when 122 is deactivated) received from the primary side controller (126).
However, Gong fails to teach (emphasis on the underlined portion) the converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator).
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Above Fig. 1, 2a-b & 2e from Arun Khamesra et al. (“Arun”, US Pat 10651753)
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35)
[Additional Examiner’s NOTE: Arun also teaches flyback converter, as seen in Fig. 1-2a including an AC input, transformer 204 with primary winding Np and secondary winding Ns; a main switch 216 driven by a primary side IC controller 218; a secondary-side synchronous rectifier MOSFET ‘226 &/or 236’ driven by a secondary side IC controller 202, via driver(s) ‘262 &/or 260’, respectively; a clamping circuit 118 on the secondary side, coupled between SR FET’s drain and SR_Sense pin of 218; wherein 202 includes a SR sense pins 228 with SR Sense 260 operation, which includes ‘NSN comparator 288, ZCD comparator 286, peak detector 190 and line feedforward 292’, along with feedback operation 272 among others controlled elements, as seen in Fig. 2b & 2e. Lastly, Arun’s Fig. 4-5 and 7-10 shows primary vs. secondary switching operation, using among others also ZCD and NSN, in order to control the current and load’s requirements.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
Regarding independent claim 12, Gong teaches (Fig. 1-4, 6; Para 18-38) an integrated circuit (IC) controller (flyback AC-DC converter 10 with primary side IC controller 126 and secondary-side IC controller 140; wherein 140 is described as 440. 10 includes a transformer 106 having a primary winding 108 coupled to a power switch 122 and a secondary winding 110 coupled to a synchronous rectifier (SR) field effect transistor (FET) 112; the primary side controller 126 coupled to control the power switch 122; and a SR controller 140 described as 440 later coupled to control the SR FET 112) comprising:
a SR sense pin to receive a drain voltage of a synchronous rectifier (SR) field effect transistor (FET) (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet);
a gate driver to send gate control signals to the SR FET (gate driver 442 driving SR FET 112’s gate);
a negative-sensing (NSN) comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38)
coupled between the SR sense pin (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) and the gate driver (gate driver 442 driving SR FET 112’s gate),
wherein the NSN comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34) is operable to generate a turn-on signal based on a voltage on the SR sense pin (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38); and
a detector comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38)
coupled between the SR sense pin (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) and the gate driver (gate driver 442 driving SR FET 112’s gate),
wherein the comparator (404 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34) is operable to generate a first turn-off signal based on the voltage on the SR sense pin (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38);
wherein the gate driver (gate driver 442 driving SR FET 112’s gate) is operable
to turn on the SR FET in response to the turn-on signal from the NSN comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112) and
to turn off the SR FET in response to the first turn-off signal from the comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112);
wherein the IC controller (140 described as 440 operates independent of 126, but does considers output of 108’s, same as Applicants Fig. 4 or 7) is operable to turn off the SR FET (turn off SR FET 112) without turn-on information of the power switch (without turn-on information of power switch 122, in another word during the period when 122 is deactivated) received from the primary side controller (126).
However, Gong fails to teach (emphasis on the underlined portion) the IC controller configured to operate in continuous conduction mode (CCM) and use of a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35).
[Additional Examiner’s NOTE: Arun also teaches flyback converter, as seen in Fig. 1-2a including an AC input, transformer 204 with primary winding Np and secondary winding Ns; a main switch 216 driven by a primary side IC controller 218; a secondary-side synchronous rectifier MOSFET ‘226 &/or 236’ driven by a secondary side IC controller 202, via driver(s) ‘262 &/or 260’, respectively; a clamping circuit 118 on the secondary side, coupled between SR FET’s drain and SR_Sense pin of 218; wherein 202 includes a SR sense pins 228 with SR Sense 260 operation, which includes ‘NSN comparator 288, ZCD comparator 286, peak detector 190 and line feedforward 292’, along with feedback operation 272 among others controlled elements, as seen in Fig. 2b & 2e. Lastly, Arun’s Fig. 4-5 and 7-10 shows primary vs. secondary switching operation, using among others also ZCD and NSN, in order to control the current and load’s requirements.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
Regarding claims 2, 13, Gong teaches the NSN comparator is configured to detect when the voltage on the SR sense pin changes from positive to negative (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38).
Regarding claims 4, 15, Gong teaches the detector comparator is configured to detect when the voltage on the SR sense pin rises above a threshold voltage (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38).
However, Gong fails to teach (emphasis on the underlined portion) the converter explicitly using the zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35).
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
Regarding claims 6, 17, Gong teaches the SR controller (140 described as 440 operates independent of 126, but does considers output of 108’s, same as Applicants Fig. 4 or 7) further comprises
an active clamping circuit (410) coupled between the SR sense pin (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) and each of the NSN comparator (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38) and the detector comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38).
wherein the active clamping circuit (410) is operable to clamp the voltage on the SR sense pin (Vdet on pin PC being clamped using 410), when the SR FET is turned onto a clamping voltage (SR sense is pin PC, coupled SR FET 112’s drain, receiving detected voltage Vdet’s rising/positive vs. falling/negative voltages; Para 21, 27, 34) below a threshold voltage (408) of the detector comparator (404).
However, Gong fails to teach (emphasis on the underlined portion) the converter explicitly using the zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35).
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
Regarding claim 11, Gong teaches an alternating current (AC) input (Vac) coupled to the primary winding (108) of the transformer (106); a direct current (DC) output (rectified DC output of 102 being Vin passed to 108 and 110, respectively) coupled to the secondary winding (108 and 110 magnetically coupled) of the transformer (106).
However, Gong fails to teach (emphasis on the underlined portion) a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of Vac).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35).
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
Claims 3, 5, 7, 8, 14, 16, 18, 19 are rejected under 35 U.S.C 103 as being unpatentable over Gong (US Pub 2015/0280584), in view of Arun (US Pat 10651753) and Tobias Heuken et al. (“Tobias”, US Pub 2014/0218978).
Regarding claims 3, 14, Gong teaches the NSN comparator is coupled to a reference voltage (402 sensing detected Vdet changes from rising/positive to falling/negative; Para 21, 27, 34. 402 is comparing a reference/threshold voltage Vref 406 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value. 402’s output triggers a start &/or delayed start signal, via other intervening elements to gate driver 442 to turn on SR FET 112. See Para 21-25 and 36-38).
However, Gong fails to teach (emphasis on the underlined portion) the reference voltage being in a range from -700 millivolts (mV) to +200 mV.
However, Tobias teaches in a flyback converter (Para 50, 53, 54) to include a technique for any type of comparison (such as ZCD &/or NSN, etc.), where the reference voltage being in any specific fixed value (Para 53), such as substantially -5 millivolts (mV) (or of 0 volts) or being in a varied ranged values (Para 53), such as from -700 millivolts (mV) to +200 mV.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter collectively taught by Gong and Arun to include a technique for any type of comparison (such as ZCD or NSN, etc.), where the reference voltage being in any specific value or being in a varied ranged valued, as doing so would have provided improved adaptability adjustment control to meet load’s requirement a much more efficient manner, as taught by Tobias (Para 53 and abstract), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claims 5, 16, Gong teaches the detector comparator is coupled to a reference voltage (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38).
However, Gong fails to teach (emphasis on the underlined portion) the converter explicitly using the zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator) and reference voltage value being substantially -5 millivolts (mV).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35) and reference voltage value (i.e., from 234 at – input of ZCD 286) being of a specific value.
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
However, Gong and Arun fail to teach use of the reference voltage value being substantially -5 millivolts (mV).
However, Tobias teaches in a flyback converter (Para 50, 53, 54) to include a technique for any type of comparison (such as ZCD &/or NSN, etc.), where the reference voltage being in any specific fixed value (Para 53), such as substantially -5 millivolts (mV) (or of 0 volts) or being in a varied ranged values (Para 53), such as from -700 millivolts (mV) to +200 mV.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter collectively taught by Gong and Arun to include a technique for any type of comparison (such as ZCD or NSN, etc.), where the reference voltage being in any specific value or being in a varied ranged valued, as doing so would have provided improved adaptability adjustment control to meet load’s requirement a much more efficient manner, as taught by Tobias (Para 53 and abstract), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 7, 18, Gong teaches the detector comparator is operable to detect within certain seconds or nanoseconds (i.e., using 410 & 404’s combined output, especially when combined with ‘424, 444, 446, 448, 452 and 440’ operation to control gate driver 442 to control SR FET 112) when the voltage on the SR sense pin rises above the threshold voltage (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38).
However, Gong fails to teach (emphasis on the underlined portion) the converter explicitly using the zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), detecting within 20 nanoseconds (ns) (when the voltage on the SR sense pin rises above the threshold voltage).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35), detecting within certain speed (when the voltage on the SR sense pin rises above the threshold voltage at – input of ZCD 286 from pin 234).
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
However, the converter collectively taught by Gong and Arun fail to teach the ZCD comparator detecting within a speed value of 20 nanoseconds (ns).
However, it would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter collectively taught by Gong and Arun to have the ZCD comparator detecting within a speed value of 20 nanoseconds (ns) (i.e., using Gong’s clamp circuit output is used by ZCD comparator as the adjusted sensed voltage from the SR sense pin rising above the threshold voltage), as disclosed by Gong, as doing so would have provided faster transient detection technique improving overall performance of the converter in a much more faster and efficient manner, as taught by Gong (Para 4-5 and abstract), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 8, 19, Gong teaches the active clamp circuit (410), the detector comparator (404 sensing detected Vdet changes from rising/positive to falling/negative, via clamping circuit 410; Para 21, 27, 34. 404 is comparing another reference/threshold voltage Vref 408 with detected voltage Vdet’s rising/positive vs. falling/negative voltages of SR sense pin PC’s +/- value; wherein 404 detects Vdet, via clamping circuit 410. 404’s output triggers a reset &/or delayed reset signal, via other intervening elements to gate driver 442 to turn off SR FET 112. See Para 21-25 and 36-38), and the gate driver (442) are operable to turn off the SR FET (to turn off SR FET 112) within certain second or nanoseconds (ns) of a rise of the voltage (Vdet, via 410) on the SR sense pin (pin PC) above the threshold or reference voltage (408).
However, Gong fails to teach (emphasis on the underlined portion) the converter explicitly using the zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator) controlling the gate driver to turn off the SR FET within 50 nanoseconds (ns) and the threshold voltage being a value volt (V).
However, Arun teaches (emphasis on the underlined portion) the converter (Fig. 1-2a; flyback converter; col. 5 L1-col. 6 L65) used as a Universal Serial Bus Power Delivery (USB-PD) converter by having a USB Type-C (USB-C) connector coupled to the DC output (rectified DC Vin of AC input) (col. 5 L43-64), wherein the converter’s IC controller is configured to operate in continuous conduction mode (CCM) (i.e., using ZCD operation to perform CCM; col. 16 L56-col. 17 L11), using a zero-crossing detector (ZCD) comparator (Fig. 2E; ZCD comparator286, operating as same as Gong’s taught detector comparator; col. 9 L35-col. 11 L35) controlling the gate driver to turn off the SR FET (226) within certain speed and the threshold voltage being of a value volt (V).
[See, above Additional Examiner’s NOTE, which is applicable here as well.]
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Gong’s converter being used as a Universal Serial Bus Power Delivery (USB-PD) converter configured to operate in continuous conduction mode (CCM), the USB-PD converter using a zero-crossing detector (ZCD) comparator (i.e., for the taught detector comparator), as disclosed by Arun, as doing so would have provided improved measuring loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the primary-side in response to the voltage sensed on the drain of the synchronous rectifier FET at or very close the primary side valley improving efficiency and performance of the converter, as taught by Arun (abstract).
However, Gong and Arun fail to teach the ZCD comparator controlling the gate driver to turn off the SR FET within certain speed being in a value of within 50 nanosecond (nS) and the threshold voltage being of a value of 0 volt (V).
However, it would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter collectively taught by Gong and Arun to have the ZCD comparator detecting within a speed value of 20 nanoseconds (ns) (i.e., using Gong’s clamp circuit output is used by ZCD comparator as the adjusted sensed voltage from the SR sense pin rising above the threshold voltage), as disclosed by Gong, as doing so would have provided faster transient detection technique improving overall performance of the converter in a much more faster and efficient manner, as taught by Gong (Para 4-5 and abstract), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
However, Tobias teaches in a flyback converter (Para 50, 53, 54) to include a technique for any type of comparison (such as ZCD &/or NSN, etc.), where the reference voltage being in any specific fixed value (Para 53), such as a value of 0 volts (or substantially -5 millivolts (mV)) or being in a varied ranged values (Para 53), such as from -700 millivolts (mV) to +200 mV.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter collectively taught by Gong and Arun to include a technique for any type of comparison (such as ZCD or NSN, etc.), where the reference voltage being in any specific value or being in a varied ranged valued, as doing so would have provided improved adaptability adjustment control to meet load’s requirement a much more efficient manner, as taught by Tobias (Para 53 and abstract), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 9-10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, cited art(s) failed to teach, the SR controller further comprises “a closed-loop differentiator circuit coupled between the SR sense pin and the gate diver, wherein the closed-loop differentiator circuit is operable to generate a second turn-off signal based on a detected change in a rise of the voltage on SR sense pin, and wherein the gate driver is further operable to turn off the SR FET in response to the second turn-off signal”.
Claim 10 depends from claim 9.
Regarding claim 20. cited art(s) failed to teach, the IC controller further comprising “a closed-loop differentiator circuit coupled between the SR sense pin and the gate diver, wherein the closed- loop differentiator circuit is operable to generate a second turn-off signal based on a detected change in a rise of the voltage on SR sense pin, and wherein the gate driver is further operable to turn off the SR FET in response to the second turn-off signal”.
Conclusion
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
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