DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2023/0170149).
In regards to claim 1, Kim ‘149 discloses
A multilayer ceramic capacitor comprising
a ceramic body (110 – fig. 2; [0026]) configured to include a dielectric layer (111 – fig. 2; [0027]) therein, and first and second internal electrodes (121 & 122 – fig. 2; [0027]) facing each other with the dielectric layer provided therebetween,
wherein the ceramic body satisfies a following conditional equation:
[Conditional Equation]
0 ≤ (a-b)/a ≤ 0.1
wherein
a: Indentation hardness (HIT) of a lower portion of the ceramic body,
b: Indentation hardness (HIT) of an upper portion of the ceramic body ([0066-0075], [0086-0088], [0093], & table 1-2 – lower and upper cover layers hardness is Hc (i.e. Hc-Hc/Hc=0) or upper cover layer hardness is Hc and lower portion hardness is H2 (i.e. a-b)/a=14.65-14.59/14.65=0.004)).
In regards to claim 2, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 1, wherein when the ceramic body is divided into two based on a distance from an upper surface to a lower surface, the lower portion of the ceramic body is a portion closest to the lower surface of the ceramic body, and
the upper portion of the ceramic body is a portion closest to the upper surface of the ceramic body (fig. 5-6; [0086-0088] & table 1-2 – lower and upper cover layers hardness is Hc (i.e. Hc-Hc/Hc=0) or upper cover layer hardness is Hc and lower portion hardness is H2 (i.e. a-b)/a=14.65-14.59/14.65=0.004)).
In regards to claim 3, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 1, wherein when the ceramic body is divided into four based on a distance from an upper surface to a lower surface, the lower portion of the ceramic body is a portion closest to the lower surface of the ceramic body, and
the upper portion of the ceramic body is a portion closest to the upper surface of the ceramic body (fig. 5-6; [0086-0088] & table 1-2 – lower and upper cover layers hardness is Hc (i.e. Hc-Hc/Hc=0) or upper cover layer hardness is Hc and lower portion hardness is H2 (i.e. a-b)/a=14.65-14.59/14.65=0.004)).
In regards to claim 4, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 1, wherein when the ceramic body is divided into three based on a distance from an upper surface to a lower surface, the lower portion of the ceramic body is a portion closest to the lower surface of the ceramic body, and
the upper portion of the ceramic body is a portion closest to the upper surface of the ceramic body (fig. 5-6; [0086-0088] & table 1-2 – lower and upper cover layers hardness is Hc (i.e. Hc-Hc/Hc=0) or upper cover layer hardness is Hc and lower portion hardness is H2 (i.e. a-b)/a=14.65-14.59/14.65=0.004)).
In regards to claim 5, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 1, wherein the ceramic body has an upper surface, which is a surface of the upper portion of the ceramic body, and a lower surface, which is a surface of the lower portion of the ceramic body, and
the upper surface is a portion to which a pressure is applied during sintering of the ceramic body (fig. 5-6; [0086-0089]).
In regards to claim 6, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 1, further comprising: a first external electrode (131 – fig. 2; [0049]) connected to the first internal electrode; and
a second external electrode (132 – fig. 2; [0049]) connected to the second internal electrode.
In regards to claim 7, Kim ‘149 discloses
A multilayer ceramic capacitor comprising:
a ceramic body (110 – fig. 2; [0026]) including a dielectric layer (111 – fig. 2; [0027]);
first and second internal electrodes (121 & 122 – fig. 2; [0027]) facing each other with the dielectric layer provided therebetween;
a first cover layer (112 – fig. 2; [0033]) disposed between an upper surface of the ceramic body and an internal electrode closest thereto; and
a second cover layer (113 – fig. 2; [0033]) disposed between an lower surface of the ceramic body and an internal electrode closest thereto,
and wherein the ceramic body satisfies the following conditional equation:
[Conditional Equation]
0 ≤ (a - b)/a ≤ 0.1
wherein
a: Indentation hardness (HIT) of a lower portion of the ceramic body, and
b: Indentation hardness (HIT) of an upper portion of the ceramic body ([0066-0075], [0086-0088], [0093], & table 1-2 – lower and upper cover layers hardness is Hc (i.e. Hc-Hc/Hc=0) or upper cover layer hardness is Hc and lower portion hardness is H2 (i.e. a-b)/a=14.65-14.59/14.65=0.004)).
In regards to claim 8, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 7, wherein the first cover layer is formed by stacking at least one dielectric layer on an uppermost internal electrode and a dielectric layer parallel to the uppermost internal electrode (fig. 4).
In regards to claim 9, Kim ‘149 discloses
The multilayer ceramic capacitor of claim 7, wherein the second cover layer is formed by stacking at least one dielectric layer under a lowermost internal electrode and a dielectric layer parallel to the lowermost internal electrode (fig. 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP2018170527A – fig. 17-18 US 2003/0016484 – [0136] & [0268]
US 2016/0053039 – abstract
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David M Sinclair/Primary Examiner, Art Unit 2847
