DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/08/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240126443), in view of Cariello (US 20220004337).
Regarding Claim 1, Kwon teaches
A memory controller, comprising: a command queue, storing a plurality of commands received from a host device, wherein the command queue comprises a plurality of slots and each slot corresponds to one command; (Kwon [0003] A memory controller controls read and write operations of a memory according to a request from a host. [0005] a memory controller includes: a request buffer suitable for storing a read request and a write request of a first rank, and a read request and a write request of a second rank) (i.e., request buffer is a command queue)
and a microprocessor, fetching the plurality of commands from the command queue and sequentially adding the plurality of commands in a handle list, wherein when sequentially adding the plurality of commands in the handle list, (Kwon [0006] an arbiter suitable for determining a first request and second requests among the stored requests [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620. FIG. 7B shows the arbiter 630 determining the issue order of the requests stored in the request buffer 620.) (i.e., arbiter determines the issue order of commands in the handle list)
the microprocessor sorts the plurality of commands in the handle list based on an order of receiving the plurality of commands and a default priority of each of the plurality of commands; (Kwon [0062] Requests may be transferred from the host HOST to the memory controller 110 through the host interface 610. [0064] the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order. [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued. [0067] the arbiter 630 may determine the issue order of the requests with the priority in the mentioned order of the A case, the B case, the C case, and the D case. When the arbiter 630 determines the issue order of the requests, the arbiter 630 may use not only the above-described policy but also other policies as well. For example, the arbiter 630 may assign 7 points to the A case, 5 points to the B case, 3 points to the C case, and 1 point to the D case, assign each case a different score according to another policy, and determine the issue order in order of the highest scores.) (i.e., sequential commands are transferred from the host and each command from host with type and rank, A/B/C/D case, is the default priority. Arbiter determines the issue order based on the default priority from host and arbiter assign points to default priority and sorts issue order in order of the highest scores.)
Kwon does not explicitly teach
wherein the default priority of each of the plurality of commands is set by the host device in an attribute field of said each of the plurality of commands.
However, Cariello teaches wherein the default priority of each of the plurality of commands is set by the host device in an attribute field of said each of the plurality of commands. host commands received from the host (Cariello [0029] The memory controller 115 is configured to receive a command and obtain an expiration time for the command. the host 105 creates the expiration time [0032] a lowest priority has a maximum expiration time [0035] the expiration time encompasses priority information [0045] priority-relevant command attributes [0046] incoming commands are given an initial expiration time, priority rules can dynamically change based on detected workload or a setting made by the host) (i.e., incoming commands from host with an initial expiration time which is a priority-relevant command attributes)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Regarding Claim 2, Kwon and Cariello teach
The memory controller of claim 1, wherein the microprocessor determines a priority score for each of the plurality of commands based on the corresponding default priority, (Kwon [0064] the arbiter 630 may give the highest priority to a request for an operation of the same type and the same rank as those of the first request, give the second highest priority to a request for an operation of a different type and a different rank from those of the first request, give the third highest priority to a request for an operation of the same type as the type of the first request in a different rank from the rank of the first request, and give the lowest priority to a request for an operation of a different type from the type of the first request in the same rank as the rank of the first request.)
and sequentially adds the plurality of commands to the handle list according to the priority score of each of the plurality of commands based on the order of receiving the plurality of commands. (Kwon [0065] The requests are received from the host in the order of (a), (b), (c), (d), (e), (f), (g), and (h). [0066] Among the requests (c) and (g), since the request (c) is received first, the request (c) may be determined as the third request to be issued)
Regarding Claim 3, Kwon and Cariello teach
The memory controller of claim 2, wherein the handle list records a slot index and the priority score of each of the plurality of commands. (Kwon [0064] The arbiter 630 may determine an issue order of the requests stored in the request buffer 620. When the issue order of the requests is determined, the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order.)
Regarding Claim 4, Kwon and Cariello teach
Kwon teaches wherein the microprocessor sorts the plurality of commands in the handle list to generate a plurality of sorted commands, and the processor further dynamically adjusts one or more of the priority scores corresponding to the plurality of sorted commands in the handle list. (Kwon [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620 [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued.)
Kwon does not teach but Cariello teaches and the processor further dynamically adjusts one or more of the priority scores (Cariello [0046] incoming commands are given an initial expiration time, priority rules can dynamically change based on detected workload or a setting made by the host)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Regarding Claim 5, Kwon and Cariello teach
The memory controller of claim 4, wherein the microprocessor sequentially executes the plurality of sorted commands from a beginning of the handle list. (Kwon [0066] Referring to FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first.)
Regarding Claim 6, Kwon and Cariello teach
Kwon does not teach but Cariello teaches wherein when an execution order of a sorted command in the handle list has been overtaken, the microprocessor raises the priority score corresponding to the sorted command. (Cariello [0012] a host entity continually specifying high priorities for commands, higher priority commands continue to be moved in front of the lower priority command, can lead to command starvation for lower priority commands. [0035] increase the priority of aging commands to address the starvation issue)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Regarding Claim 7, Kwon and Cariello teach
The memory controller of claim 1, further comprising: a buffer memory, storing the handle list and the plurality of commands, wherein each slot of the command queue stores information regarding a storage address of the corresponding command in the buffer memory. (Kwon [0061] the memory controller 110 may include a host interface 610, a request buffer 620, an arbiter 630, a command generator 640, and a memory interface 650. [0069] The memory interface 650 may contribute to transferring commands and addresses from the memory controller 110 to the memories 120)
Regarding Claim 9, Kwon teaches
A method for sorting commands, comprising: receiving a plurality of commands from a host device and storing the plurality of commands in a command queue, wherein the command queue comprises a plurality of slots and each slot corresponds to one command;
(Kwon [0003] A memory controller controls read and write operations of a memory according to a request from a host. [0005] a memory controller includes: a request buffer suitable for storing a read request and a write request of a first rank, and a read request and a write request of a second rank) (i.e., request buffer is a command queue)
and sequentially adding the plurality of commands in a handle list, wherein step of sequentially adding the plurality of commands in the handle list further comprises:
(Kwon [0006] an arbiter suitable for determining a first request and second requests among the stored requests [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620. FIG. 7B shows the arbiter 630 determining the issue order of the requests stored in the request buffer 620.) (i.e., arbiter determines the issue order of commands in the handle list)
sorting the plurality of commands in the handle list based on an order of receiving the plurality of commands and a default priority of each of the plurality of commands; (Kwon [0062] Requests may be transferred from the host HOST to the memory controller 110 through the host interface 610. [0064] the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order. [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued. [0067] the arbiter 630 may determine the issue order of the requests with the priority in the mentioned order of the A case, the B case, the C case, and the D case. When the arbiter 630 determines the issue order of the requests, the arbiter 630 may use not only the above-described policy but also other policies as well. For example, the arbiter 630 may assign 7 points to the A case, 5 points to the B case, 3 points to the C case, and 1 point to the D case, assign each case a different score according to another policy, and determine the issue order in order of the highest scores.) (i.e., sequential commands are transferred from the host and each command from host with type and rank, A/B/C/D case, is the default priority. Arbiter determines the issue order based on the default priority from host and arbiter assign points to default priority and sorts issue order in order of the highest scores.)
Kwon does not explicitly teach
wherein the default priority of each of the plurality of commands is set by the host device in an attribute field of said each of the plurality of commands.
However, Cariello teaches wherein the default priority of each of the plurality of commands is set by the host device in an attribute field of said each of the plurality of commands. host commands received from the host (Cariello [0029] The memory controller 115 is configured to receive a command and obtain an expiration time for the command. the host 105 creates the expiration time [0032] a lowest priority has a maximum expiration time [0035] the expiration time encompasses priority information [0045] priority-relevant command attributes [0046] incoming commands are given an initial expiration time, priority rules can dynamically change based on detected workload or a setting made by the host) (i.e., incoming commands from host with an initial expiration time which is a priority-relevant command attributes)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Regarding Claim 10, Kwon and Cariello teach
The method of claim 9, wherein step of sorting the plurality of commands in the handle list based on the order of receiving the plurality of commands and the default priority of each of the plurality of commands further comprises: determining a priority score for each of the plurality of commands based on the corresponding default priority; (Kwon [0064] the arbiter 630 may give the highest priority to a request for an operation of the same type and the same rank as those of the first request, give the second highest priority to a request for an operation of a different type and a different rank from those of the first request, give the third highest priority to a request for an operation of the same type as the type of the first request in a different rank from the rank of the first request, and give the lowest priority to a request for an operation of a different type from the type of the first request in the same rank as the rank of the first request.)
and sequentially adding the plurality of commands to the handle list according to the priority score of each of the plurality of commands based on the order of receiving the plurality of commands. (Kwon [0065] The requests are received from the host in the order of (a), (b), (c), (d), (e), (f), (g), and (h). [0066] Among the requests (c) and (g), since the request (c) is received first, the request (c) may be determined as the third request to be issued)
Regarding Claim 11, Kwon and Cariello teach
The method of claim 10, wherein the handle list records a slot index and the priority score of each of the plurality of commands. (Kwon [0064] The arbiter 630 may determine an issue order of the requests stored in the request buffer 620. When the issue order of the requests is determined, the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order.)
Regarding Claim 12, Kwon and Cariello teach
Kwon teaches wherein step of sorting the plurality of commands in the handle list based on the order of receiving the plurality of commands and the default priority of each of the plurality of commands further comprises: dynamically adjusting one or more of the priority scores corresponding to a plurality of sorted commands in the handle list, wherein the plurality of sorted commands in the handle list are generated by sorting the plurality of commands in the handle list. (Kwon [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620 [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued.)
Kwon does not teach but Cariello teaches dynamically adjusting one or more of the priority scores (Cariello [0046] incoming commands are given an initial expiration time, priority rules can dynamically change based on detected workload or a setting made by the host)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Regarding Claim 13, Kwon and Cariello teach
The method of claim 12, wherein the plurality of sorted commands are executed from a beginning of the handle list. (Kwon [0066] Referring to FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first.)
Regarding Claim 14, Kwon and Cariello teach
Kwon does not teach but Cariello teaches wherein step of dynamically adjusting one or more of the priority scores corresponding to the plurality of sorted commands in the handle list further comprises: raising the priority score corresponding to a sorted command when an execution order of the sorted command in the handle list has been overtaken. (Cariello [0012] a host entity continually specifying high priorities for commands, higher priority commands continue to be moved in front of the lower priority command, can lead to command starvation for lower priority commands. [0035] increase the priority of aging commands to address the starvation issue)
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Shen (US 20220317934) teaches efficient memory access scheduling, increases priority of older commands
Response to Arguments
Applicant's arguments filed 09/08/2026 have been fully considered but they are not persuasive.
Applicant argued that cited reference does not teach amendment limitations. The Office
respectfully disagrees.
The amended limitations are addressed in new rejection based on the amendment.
First, for claim 1, the combination of Kwon and Cariello discloses the limitations of claim 1.
Kwon and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Cariello to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Cariello’s teaching of dynamically change the default priority from host. The motivation for doing so would be to (Cariello [0035, 0017]) increase the priority of aging commands to address the starvation issue without additional processing by the memory controller, to avoid low-priority command starvation.
Next, for claim 9, Applicant argues as similar to claim 1.
Applicant’s argument for dependent claims 2-7 and 10-14 are based on their respective base independent claim 1 and 9, which are addressed above.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
