DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-11, 15 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kwon (US 20240126443).
Regarding Claim 1, Kwon teaches
A memory controller, comprising: a command queue, storing a plurality of commands received from a host device, wherein the command queue comprises a plurality of slots and each slot corresponds to one command; (Kwon [0003] A memory controller controls read and write operations of a memory according to a request from a host. [0005] a memory controller includes: a request buffer suitable for storing a read request and a write request of a first rank, and a read request and a write request of a second rank)
and a microprocessor, fetching the plurality of commands from the command queue and sequentially adding the plurality of commands in a handle list, wherein when sequentially adding the plurality of commands in the handle list, (Kwon [0006] an arbiter suitable for determining a first request and second requests among the stored requests [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620)
the microprocessor sorts the plurality of commands in the handle list based on an order of receiving the plurality of commands and a default priority of each of the plurality of commands. (Kwon [0062] Requests may be transferred from the host HOST to the memory controller 110 through the host interface 610. [0064] the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order. [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued. [0067] the arbiter 630 may determine the issue order of the requests with the priority in the mentioned order of the A case, the B case, the C case, and the D case. When the arbiter 630 determines the issue order of the requests, the arbiter 630 may use not only the above-described policy but also other policies as well. For example, the arbiter 630 may assign 7 points to the A case, 5 points to the B case, 3 points to the C case, and 1 point to the D case, assign each case a different score according to another policy, and determine the issue order in order of the highest scores.) (i.e., sequential commands are transferred from the host and each command from host with type and rank, A/B/C/D case, is the default priority. Arbiter determines the issue order based on the default priority from host and arbiter assign points to default priority and sorts issue order in order of the highest scores.)
Regarding Claim 2, Kwon teaches
Kwon teaches wherein the microprocessor determines a priority score for each of the plurality of commands based on the corresponding default priority, (Kwon [0064] the arbiter 630 may give the highest priority to a request for an operation of the same type and the same rank as those of the first request, give the second highest priority to a request for an operation of a different type and a different rank from those of the first request, give the third highest priority to a request for an operation of the same type as the type of the first request in a different rank from the rank of the first request, and give the lowest priority to a request for an operation of a different type from the type of the first request in the same rank as the rank of the first request.)
and sequentially adds the plurality of commands to the handle list according to the priority score of each of the plurality of commands based on the order of receiving the plurality of commands. (Kwon [0065] The requests are received from the host in the order of (a), (b), (c), (d), (e), (f), (g), and (h). [0066] Among the requests (c) and (g), since the request (c) is received first, the request (c) may be determined as the third request to be issued)
Regarding Claim 3, Kwon teaches
Kwon teaches wherein the handle list records a slot index and the priority score of each of the plurality of commands. (Kwon [0064] The arbiter 630 may determine an issue order of the requests stored in the request buffer 620. When the issue order of the requests is determined, the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order.)
Regarding Claim 7, Kwon teaches
The memory controller of claim 1, further comprising: a buffer memory, storing the handle list and the plurality of commands, wherein each slot of the command queue stores information regarding a storage address of the corresponding command in the buffer memory. (Kwon [0061] the memory controller 110 may include a host interface 610, a request buffer 620, an arbiter 630, a command generator 640, and a memory interface 650. [0069] The memory interface 650 may contribute to transferring commands and addresses from the memory controller 110 to the memories 120)
Regarding Claim 8, Kwon teaches
Kwon teaches wherein the default priority of each of the plurality of commands is set by the host device. (Kwon [0063] The request buffer 620 may store the requests transferred from the host HOST to the memory controller 110. The requests may include a read request of the first rank, a write request of the first rank, a read request of the second rank, and a write request of the second rank.)
Regarding Claim 9, Kwon teaches
A method for sorting commands, comprising: receiving a plurality of commands from a host device and storing the plurality of commands in a command queue, wherein the command queue comprises a plurality of slots and each slot corresponds to one command;
(Kwon [0003] A memory controller controls read and write operations of a memory according to a request from a host. [0005] a memory controller includes: a request buffer suitable for storing a read request and a write request of a first rank, and a read request and a write request of a second rank)
and sequentially adding the plurality of commands in a handle list, wherein step of sequentially adding the plurality of commands in the handle list further comprises:
(Kwon [0006] an arbiter suitable for determining a first request and second requests among the stored requests [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620)
sorting the plurality of commands in the handle list based on an order of receiving the plurality of commands and a default priority of each of the plurality of commands. (Kwon [0062] Requests may be transferred from the host HOST to the memory controller 110 through the host interface 610. [0064] the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order. [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued. [0067] the arbiter 630 may determine the issue order of the requests with the priority in the mentioned order of the A case, the B case, the C case, and the D case. When the arbiter 630 determines the issue order of the requests, the arbiter 630 may use not only the above-described policy but also other policies as well. For example, the arbiter 630 may assign 7 points to the A case, 5 points to the B case, 3 points to the C case, and 1 point to the D case, assign each case a different score according to another policy, and determine the issue order in order of the highest scores.) (i.e., sequential commands are transferred from the host and each command from host with type and rank, A/B/C/D case, is the default priority. Arbiter determines the issue order based on the default priority from host and arbiter assign points to default priority and sorts issue order in order of the highest scores.)
Regarding Claim 10, Kwon teaches
Kwon teaches wherein step of sorting the plurality of commands in the handle list based on the order of receiving the plurality of commands and the default priority of each of the plurality of commands further comprises: determining a priority score for each of the plurality of commands based on the corresponding default priority; (Kwon [0064] the arbiter 630 may give the highest priority to a request for an operation of the same type and the same rank as those of the first request, give the second highest priority to a request for an operation of a different type and a different rank from those of the first request, give the third highest priority to a request for an operation of the same type as the type of the first request in a different rank from the rank of the first request, and give the lowest priority to a request for an operation of a different type from the type of the first request in the same rank as the rank of the first request.)
and sequentially adding the plurality of commands to the handle list according to the priority score of each of the plurality of commands based on the order of receiving the plurality of commands. (Kwon [0065] The requests are received from the host in the order of (a), (b), (c), (d), (e), (f), (g), and (h). [0066] Among the requests (c) and (g), since the request (c) is received first, the request (c) may be determined as the third request to be issued)
Regarding Claim 11, Kwon teaches
Kwon teaches wherein the handle list records a slot index and the priority score of each of the plurality of commands. (Kwon [0064] The arbiter 630 may determine an issue order of the requests stored in the request buffer 620. When the issue order of the requests is determined, the arbiter 630 may determine the issue order of the requests with a priority of A case, B case, C case, and D case in the mentioned order.)
Regarding Claim 15, Kwon teaches
Kwon teaches wherein the default priority of each of the plurality of commands is set by the host device. (Kwon [0063] The request buffer 620 may store the requests transferred from the host HOST to the memory controller 110. The requests may include a read request of the first rank, a write request of the first rank, a read request of the second rank, and a write request of the second rank.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240126443), in view of Shen (US 20220317934).
Regarding Claim 4, Kwon teaches
Kwon teaches wherein the microprocessor sorts the plurality of commands in the handle list to generate a plurality of sorted commands, and the processor further dynamically adjusts one or more of the priority scores corresponding to the plurality of sorted commands in the handle list. (Kwon [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620 [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued.)
Kwon does not teach and the processor further dynamically adjusts one or more of the priority scores
However, Shen teaches the processor further dynamically adjusts one or more of the priority scores (Shen [0012] A memory controller includes a command queue and an arbiter. The command queue is for receiving and storing decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command. [0047] the process increases the priority and/or age of the older write commands stored in command queue)
Kwon and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Shen to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Shen’s teaching of increase the priority of the older command. The motivation for doing so would be (Shen [0004]) preserving memory controller efficiency.
Regarding Claim 5, Kwon and Shen teach
Kwon teaches wherein the microprocessor sequentially executes the plurality of sorted commands from a beginning of the handle list. (Kwon [0066] Referring to FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first.)
Regarding Claim 6, Kwon and Shen teach
Kwon does not teach but Shen teaches wherein when an execution order of a sorted command in the handle list has been overtaken, the microprocessor raises the priority score corresponding to the sorted command. (Shen [0045] [0045] In order to reduce read latency, the inventors have developed a mechanism known as dynamic latency aware write (DLAW) picking to reduce average read latency. The memory controller implements DLAW picking by elevating the priority of older write accesses stored in the command queue in response to detecting the presence of a read command to the same memory region. In this way, an older write command will be issued sooner than it would otherwise have been [0047] the process increases the priority and/or age of the older write commands stored in command queue)
Kwon and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Shen to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Shen’s teaching of increase the priority of the older command. The motivation for doing so would be (Shen [0004]) preserving memory controller efficiency.
Regarding Claim 12, Kwon teaches
Kwon teaches wherein step of sorting the plurality of commands in the handle list based on the order of receiving the plurality of commands and the default priority of each of the plurality of commands further comprises: dynamically adjusting one or more of the priority scores corresponding to a plurality of sorted commands in the handle list, wherein the plurality of sorted commands in the handle list are generated by sorting the plurality of commands in the handle list. (Kwon [0065] FIG. 7A shows requests transferred from the host that are stored in the request buffer 620 [0066] FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first…a request (f), which is a request for an operation of the same type and the same rank as the type and rank of the request (a). Therefore, the request (f) may be determined as the second request to be issued…. Finally, the request (h) which is for an operation of the same type and the same rank as the type and rank of the request (d) may be determined as the eighth request to be issued.)
Kwon does not teach dynamically adjusting one or more of the priority scores
However, Shen teaches dynamically adjusting one or more of the priority scores (Shen [0012] A memory controller includes a command queue and an arbiter. The command queue is for receiving and storing decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command. [0047] the process increases the priority and/or age of the older write commands stored in command queue)
Kwon and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Shen to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Shen’s teaching of increase the priority of the older command. The motivation for doing so would be (Shen [0004]) preserving memory controller efficiency.
Regarding Claim 13, Kwon and Shen teach
Kwon teaches wherein the plurality of sorted commands are executed from a beginning of the handle list. (Kwon [0066] Referring to FIG. 7B, the arbiter 630 may determine a request (a), which is the first request transferred from the host HOST, as a first request to be issued first.)
Regarding Claim 14, Kwon and Shen teach
Kwon does not teach but Shen teaches wherein step of dynamically adjusting one or more of the priority scores corresponding to the plurality of sorted commands in the handle list further comprises: raising the priority score corresponding to a sorted command when an execution order of the sorted command in the handle list has been overtaken. (Shen [0045] [0045] In order to reduce read latency, the inventors have developed a mechanism known as dynamic latency aware write (DLAW) picking to reduce average read latency. The memory controller implements DLAW picking by elevating the priority of older write accesses stored in the command queue in response to detecting the presence of a read command to the same memory region. In this way, an older write command will be issued sooner than it would otherwise have been [0047] the process increases the priority and/or age of the older write commands stored in command queue)
Kwon and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Kwon and Shen to modify the Kwon‘s system of managing memory access command based on priority and order of receiving with Shen’s teaching of increase the priority of the older command. The motivation for doing so would be (Shen [0004]) preserving memory controller efficiency.
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant argued that Kwon does not anticipate the default priority. The Office
respectfully disagrees.
Applicant argues “For Kwon, the arbiter dynamically calculates a relative priority for
subsequent requests based on their operation type (Read/Write) and target rank (Rank 0/1) related to the currently executing command… That is, Kwon determines execution order by dynamically comparing operational relationships between commands to minimize bus turnaround time, not by sorting commands based on a preset “default priority” belonging to each command. For the present disclosure, the “default priority” is an attribute explicitly set by the host device independent of the operation type or target address. … the Applicant believes that Kwon fails to explicitly teach the claimed limitation "wherein when sequentially adding the plurality of commands in the handle list, the microprocessor sorts the plurality of commands in the handle list based on an order of receiving the plurality of commands and a default priority of each of the plurality of commands" in claim 1”.
The Office submits that claims are given their broadest reasonable interpretation consistent with the disclosure. MPEP 2111 says claims must be given their broadest reasonable interpretation in light of the specification and imitations of the specification are not to be read into the claims.
Applicant is arguing limitations on default priority that are not recited in the claims, for example, the default being an attribute explicitly set by the host device. The Office submits that Kwon’s teaching is within the BRI of default priority. Anything that is a normal way of setting priority could be considered to be a default priority because it’s what the system does by default. Kwon teaches sequential commands are transferred from the host and each command from host with type and rank, A/B/C/D case, and the priority determined is the default priority. Arbiter determines the issue order based on the default priority from host and arbiter assign points to default priority and sorts issue order in order of the highest scores.
Therefore, for claim 1, the Office submits that Kwon teaches a default priority.
Next, for claim 9, Applicant argues as similar to claim 1.
Applicant’s argument for dependent claims 2-8 and 10-15 are based on their respective base independent claim 1 and 9, which are addressed above.
Therefore, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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