DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1 - 9 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Pelley et al. (US Pub No. 20050276141), hereinafter "Pelley", in view of Agarwal et al. (US Pub No. 20210141692), hereinafter "Agarwal" ].
As per claim 1, Pelley significantly teaches a memory device comprising (FIG. 1 illustrates, in block diagram form, an integrated circuit memory 10 ... Memory array 12 includes memory arrays, or banks, 14, 16, 18, and 20. [Pelley PP 0018]):
each bank including two sub-banks, each sub-bank including a plurality of memory cells (the burst data is interleaved between two memory sub-banks of the selected bank, for example, two equal portions, or array halves 15 and 17 of memory cell bank 14 [Pelley PP 0014] the array halves 15 and 17 are memory cell bank halves inherently including a plurality of memory cells); and
a peripheral circuit configured to receive a first control signal and a data chunk from an external device (Differential address signals CA/CA* [Pelley PP 0023], write data buffer 54 [Pelley PP 0025]),
and store the data chunk to be distributed in at least two or more sub-banks selected from among sub-banks included in the plurality of bank groups (the burst data is interleaved between two memory sub-banks of the selected bank [Pelley PP 0025]).
Pelley does not explicitly teach “a plurality of bank groups, each bank group including a plurality of banks”
However, Agarwal, in an analogous art, teaches a plurality of bank groups, each bank group including a plurality of banks (another partitioning of memory, such as by devices or banks [Agarwal PP 0035])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 2, Pelley significantly teaches wherein the peripheral circuit is configured to select one bank from among banks of the plurality of bank groups, based on the first control signal (row and column decoders for selecting a memory cell in response to receiving an address [Pelley PP 0019], Differential address signals CA/CA* [Pelley PP 0023]), and store the data chunk to be distributed in two sub-banks in the selected bank (the burst data is interleaved between two memory sub-banks of the selected bank [Pelley PP 0025]).
As per claim 3, Pelley significantly teaches wherein the first control signal comprises a first address (address buffer 42 [Pelley PP 0042]), and wherein the peripheral circuit is further configured to: select a first bank based on a part of the first address (row and column decoders for selecting a memory cell in response to receiving an address [Pelley PP 0019]), and store a half of the data chunk in each of the two sub-banks of the selected first bank, based on a remaining part of the first address (Specifically, in the case of a 256 bit cache line burst, 128 bits are burst from sub-array 15 and 128 bits are burst from sub-array 17 [Pelley PP 0025]).
As per claim 4, Pelley significantly teaches wherein the peripheral circuit is further configured to receive a second control signal from the external device (Differential address signals CA/CA* [Pelley PP 0023] are received by transceiver 56), and read the data chunk stored from two sub-banks in the selected bank based on the second control signal (Read data buffer 52 provides the data to transceiver 56 [Pelley PP 0025]).
As per claim 5, Pelley does not explicitly teach “wherein the peripheral circuit is configured to select two banks from among banks of the plurality of bank groups, based on the first control signal, and store the data chunk to be distributed in four sub-banks in the selected two banks.”
However, Agarwal, in an analogous art, teaches wherein the peripheral circuit is configured to select two banks from among banks of the plurality of bank groups, based on the first control signal, and store the data chunk to be distributed in four sub-banks in the selected two banks (the access is split over twice as many DRAMs, with 16 DRAMs being accessed for the full 512b of data [Agarwal PP 0050] splitting over twice as many resources).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 6, Pelley does not explicitly teach “wherein the selected two banks are included in the same bank group.”
However, Agarwal, in an analogous art, teaches wherein the selected two banks are included in the same bank group (another partitioning of memory, such as by devices or banks [Agarwal PP 0035]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 7, Pelley does not explicitly teach “wherein the first control signal comprises a second address, and wherein the peripheral circuit is further configured to: select a first bank group based on a first part of the second address, select a first bank and a second bank among the plurality of banks in the first bank group based on a second part of the second address, and store a quarter of the data chunk in each of two sub-banks of the first bank and two sub-banks of the second bank based on a remaining part of the second address.”
However, Agarwal, in an analogous art, teaches wherein the first control signal comprises a second address, and wherein the peripheral circuit is further configured to: select a first bank group based on a first part of the second address (split line access can be performed over multiple parallel memory resources [Agarwal PP 0026] address decoding inherent),
select a first bank and a second bank among the plurality of banks in the first bank group based on a second part of the second address (the access is split over twice as many DRAMs [Agarwal PP 0050]), and
store a quarter of the data chunk in each of two sub-banks of the first bank and two sub-banks of the second bank based on a remaining part of the second address (For example, by splitting cacheline across two different ranks [Agarwal PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 8, Pelley does not explicitly teach “wherein the peripheral circuit is configured to select one bank group among the plurality of bank groups based on the first control signal, and store the data chunk to be distributed in eight sub-banks in four banks in the selected bank group.”
However, Agarwal, in an analogous art, teaches wherein the peripheral circuit is configured to select one bank group among the plurality of bank groups based on the first control signal (another partitioning of memory, such as by devices or banks [Agarwal PP 0035]), and store the data chunk to be distributed in eight sub-banks in four banks in the selected bank group (the access is split over twice as many DRAMs, with 16 DRAMs being accessed for the full 512b of data [Agarwal PP 0050]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 9, Pelley does not explicitly teach “wherein the first control signal comprises a third address, and wherein the peripheral circuit is configured to: select a first bank group based on a first part of the third address, store one-eighth of the data chunk in each of two sub-banks in four banks in the first bank group based on a second part of the third address.”
However, Agarwal, in an analogous art, teaches wherein the first control signal comprises a third address, and wherein the peripheral circuit is configured to: select a first bank group based on a first part of the third address (split line access can be performed over multiple parallel memory resources [Agarwal PP 0026] address decoding inherent), store one-eighth of the data chunk in each of two sub-banks in four banks in the first bank group based on a second part of the third address (For example, by splitting cacheline across two different ranks [Agarwal PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
Claim(s) [ 10 - 20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Pelley in view of Agarwal, in further view of Niu et al. (US Pub No. 20180046541), hereinafter "Niu" ].
As per claim 10, Pelley significantly teaches wherein each of the plurality of first memory devices and the second memory device comprises: a plurality of bank groups, each bank group including a plurality of banks, each bank including two sub-banks, each sub-bank including a plurality of memory cells (Memory array 12 includes memory arrays, or banks, 14, 16, 18, and 20 [Pelley PP 0018], the burst data is interleaved between two memory sub-banks of the selected bank, for example, two equal portions, or array halves 15 and 17 of memory cell bank 14 [Pelley PP 0025]), and
wherein the peripheral circuit is configured to store the data chunk and the error correction code to be distributed in at least two or more sub-banks selected from among sub-banks included in the plurality of bank groups in each of the plurality of first memory devices and the second memory device (the burst data is interleaved between two memory sub-banks of the selected bank [Pelley PP 0025]).
Pelley does not explicitly teach “A data storage device comprising: a plurality of first memory devices for storing a data chunk; a second memory device for storing an error correction code generated based on the data chunk; and a peripheral circuit configured to receive a first control signal from an external device and control the plurality of first memory devices and the second memory device”
However, Agarwal, in an analogous art, teaches a plurality of first memory devices for storing a data chunk (8 memory devices for user data [Agarwal PP 0019])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
Pelley in view of Agarwal do not explicitly teach “A data storage device comprising (DRAM 160 [Niu PP 0056]): a plurality of first memory devices for storing a data chunk; a second memory device for storing an error correction code generated based on the data chunk; and a peripheral circuit configured to receive a first control signal from an external device and control the plurality of first memory devices and the second memory device”
However, Niu, in an analogous art, teaches A data storage device comprising (DRAM 160 [Niu PP 0056]):
a second memory device for storing an error correction code generated based on the data chunk (a single 4-bit ECC chip (e.g., one parity device, or parity chip) 140 b per memory channel 150 for transferring ECC data to the memory controller 110 [Niu PP 0057]); and
a peripheral circuit configured to receive a first control signal from an external device and control the plurality of first memory devices and the second memory device (memory controller 110 conducts memory transactions 130 [Niu PP 0056])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system of Pelley and Agarwal to include Niu's teaching of implementing the memory devices as four data chips and one ECC chip, in order to provide a practical memory module architecture with efficient error correction and reduced overhead (embodiments of the present invention provide an architecture capable of providing basic chipkill RAS features, like those provided by DDR4, while providing these features with reduced (e.g., minimal) ECC chip overhead [Niu PP 0101]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley and Agarwal's invention.
As per claim 11, Pelley significantly teaches wherein the peripheral circuit is further configured to select one bank from among banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device, based on the first control signal (the burst data is interleaved between two memory sub-banks of the selected bank [Pelley PP 0025] implying selection of the "selected bank")
Pelley does not explicitly teach “store the data chunk and the error correction code to be distributed In two sub-banks in the selected bank.”
However, Agarwal, in an analogous art, teaches store the data chunk and the error correction code to be distributed In two sub-banks in the selected bank (For example, by splitting cacheline across two different ranks [Agarwal PP 0026]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 12, Pelley significantly teaches wherein the first control signal comprises a first address (address buffer 42 [Pelley PP 0023]), and wherein the peripheral circuit is further configured to: select a first bank from each of the plurality of first memory devices and the second memory device based on a part of the first address (row and column decoders for selecting a memory cell in response to receiving an address [Pelley PP 0019]), and store the data chunk and the error correction code in two sub-banks of the selected first bank, based on a remaining part of the first address (Specifically, in the case of a 256 bit cache line burst, 128 bits are burst from sub-array 15 and 128 bits are burst from sub-array 17 [Pelley PP 0025]).
As per claim 13, Pelley significantly teaches wherein the peripheral circuit is further configured to: receive a second control signal from the external device (row and column decoders for selecting a memory cell in response to receiving an address [Pelley PP 0019], Differential address signals CA/CA* [Pelley PP 0023]), and read the data chunk and the error correction code stored from two sub-banks in the selected bank based on the second control signal (Read data buffer 52 provides the data to transceiver 56 [Pelley PP 0025]).
As per claim 14, Pelley does not explicitly teach “wherein the peripheral circuit is further configured to: select two banks from among banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and store the data chunk and the error correction code to be distributed in four sub- banks in the selected two banks.”
However, Agarwal, in an analogous art, teaches wherein the peripheral circuit is further configured to: select two banks from among banks of the plurality of bank groups in each of the plurality of first memory devices and the second memory device based on the first control signal, and store the data chunk and the error correction code to be distributed in four sub- banks in the selected two banks (the access is split over twice as many DRAMs, with 16 DRAMs being accessed for the full 512b of data [Agarwal PP 0050] splitting over twice as many resources).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 15, Pelley does not explicitly teach “wherein the peripheral circuit is further configured to: select one bank group among the plurality of bank groups from each of the plurality of first memory devices and the second memory device based on the first control signal, and store the data chunk and the error correction code to be distributed in eight sub-banks of four banks in the selected bank group.”
However, Agarwal, in an analogous art, teaches wherein the peripheral circuit is further configured to: select one bank group among the plurality of bank groups from each of the plurality of first memory devices and the second memory device based on the first control signal, and store the data chunk and the error correction code to be distributed in eight sub-banks of four banks in the selected bank group (the access is split over twice as many DRAMs, with 16 DRAMs being accessed for the full 512b of data [Agarwal PP 0050]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 16, Pelley in view of Agarwal do not explicitly teach “wherein the number of the plurality of first memory devices is 4.”
However, Niu, in an analogous art, teaches wherein the number of the plurality of first memory devices is 4 (four 8-bit DRAM chips 440 a to store data [Niu PP 0072]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system of Pelley and Agarwal to include Niu's teaching of implementing the memory devices as four data chips and one ECC chip, in order to provide a practical memory module architecture with efficient error correction and reduced overhead (embodiments of the present invention provide an architecture capable of providing basic chipkill RAS features, like those provided by DDR4, while providing these features with reduced (e.g., minimal) ECC chip overhead [Niu PP 0101]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley and Agarwal's invention.
As per claim 17, Pelley does not explicitly teach “wherein a size of the data chunk is calculated by multiplying a burst length (N) and 32 bits, and a size of the error correction code is calculated by multiplying a burst length (N) and 8 bits.”
However, Agarwal, in an analogous art, teaches wherein a size of the data chunk is calculated by multiplying a burst length (N) and 32 bits (8 data devices will provide 512 bits (8*64) [Agarwal PP 0020] with BL16, 512/16 = 32 bits), and a size of the error correction code is calculated by multiplying a burst length (N) and 8 bits (2 ECC devices (which can also be referred to as redundant devices) provide 128 bits (2*64) [Agarwal PP 0020] with BL16, 128/16 = 8 bits).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device disclosed by Pelley to incorporate Agarwal's teaching of distributing a data chunk across multiple banks and bank groups, in order to reduce the number of error bits per data chunk and free up memory capacity for metadata (if a cacheline read fetches less data from each memory device, the number of ECC bits required to correct a device failure will be reduced [Agarwal PP 0050]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley's invention.
As per claim 18, Pelley in view of Agarwal do not explicitly teach “wherein each of the plurality of first memory devices and the second memory device is configured to simultaneously receive or output eight bits.”
However, Niu, in an analogous art, teaches wherein each of the plurality of first memory devices and the second memory device is configured to simultaneously receive or output eight bits (8-bit DRAM chips 440 [Niu PP 0072]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system of Pelley and Agarwal to include Niu's teaching of implementing the memory devices as four data chips and one ECC chip, in order to provide a practical memory module architecture with efficient error correction and reduced overhead (embodiments of the present invention provide an architecture capable of providing basic chipkill RAS features, like those provided by DDR4, while providing these features with reduced (e.g., minimal) ECC chip overhead [Niu PP 0101]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley and Agarwal's invention.
As per claim 19, Pelley in view of Agarwal do not explicitly teach “wherein the peripheral circuit sequentially receives 40-bit data signals from the external device for as many tines as a number corresponding to the burst length.”
However, Niu, in an analogous art, teaches wherein the peripheral circuit sequentially receives 40-bit data signals from the external device for as many tines as a number corresponding to the burst length (four 8-bit DRAM chips 440 a to store data, and one 8-bit DRAM chip 440 b to store system ECC. [Niu PP 0072]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system of Pelley and Agarwal to include Niu's teaching of implementing the memory devices as four data chips and one ECC chip, in order to provide a practical memory module architecture with efficient error correction and reduced overhead (embodiments of the present invention provide an architecture capable of providing basic chipkill RAS features, like those provided by DDR4, while providing these features with reduced (e.g., minimal) ECC chip overhead [Niu PP 0101]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley and Agarwal's invention.
As per claim 20, Pelley in view of Agarwal do not explicitly teach “wherein the peripheral circuit sequentially transfers 8 bits at a time to each of the plurality of first memory devices and the second memory device.”
However, Niu, in an analogous art, teaches wherein the peripheral circuit sequentially transfers 8 bits at a time to each of the plurality of first memory devices and the second memory device (8-bit DRAM chips 440 [Niu PP 0072]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory system of Pelley and Agarwal to include Niu's teaching of implementing the memory devices as four data chips and one ECC chip, in order to provide a practical memory module architecture with efficient error correction and reduced overhead (embodiments of the present invention provide an architecture capable of providing basic chipkill RAS features, like those provided by DDR4, while providing these features with reduced (e.g., minimal) ECC chip overhead [Niu PP 0101]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Pelley and Agarwal's invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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