DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patronas et al (Pub #US 20240064443 A1) further in view of Sharply et al (pub# US 20220100598 A1).
Regarding claim 1, Patronas discloses an interface control device (transceiver 210 running on local clock 240, figure 2, paragraph 38) comprising: a clock domain crossing (CDC) circuit configured to receive (clock domain crossing, paragraph 41), from an external device (device 206 running on network clock 250, figure 2), a first signal synchronized with a first clock (bitstream with a network clock 250), and output a second signal corresponding to the first signal synchronized with a second clock (bitstream converted with CDC to the local clock 240, paragraph 41).
Patronas does not disclose explicitly using a multiplexer for subsequent signal processing. However, Sharply discloses a demultiplexer configured to divide the second signal into a plurality of signals to generate configuration information corresponding to the plurality of signals (selectively direct signals to configuration registers 510, paragraph 82); a configuration register configured to store the configuration information (paragraph 82); and an interface controller configured to operate according to the configuration information stored in the configuration register (request logic retrieves information from the configuration registers and performs corresponding commands, paragraph 84). Furthermore, teachings of Patronas and Sharply are from the same field of digital signal processing.
Therefore, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to combine teachings of Patronas and Sharply by using a demultiplexer to separate signals for the benefit of directing data to appropriate locations (paragraph 82, Sharply).
3. The interface control device of claim 1, wherein the external device is configured to operate in a first clock domain based on the first clock, and the interface controller is configured to operate in a second clock domain based on the second clock.
4. The interface control device of claim 1, wherein the interface control device is configured to communicate with the external device based on at least one of a non-coherent protocol, a coherent protocol, and a memory access protocol (examiner notes that the protocol used inherently is either non-coherent, or coherent).
5. The interface control device of claim 1, wherein the interface control device is configured to communicate with the external device based on a compute express link (CXL) protocol (examiner takes official notice that CXL was a well-known protocol before the effective filing data of the invention, and would have been obvious for a person of ordinary skill in the art to use for the benefit of conforming to well-known standards).
Regarding claims 6, 8-11, 13-16, examiner notes that these claims are substantially similar to claims 1, 3-5 above. The same grounds of rejection are applied.
Allowable Subject Matter
Claims 2, 7, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: prior art of record discloses clock domain crossing circuits and demultiplexers used to separate configuration data and store the data into register for controlling a processor. However, prior art of record does not teach or suggest, inter alia, that the demultiplexer is configured to divide a first number of the second signal from the clock domain crossing circuit into a number of plurality of signals greater than the first number. Prior art of record further does not teach or suggest, inter alia, that the second device includes a stacked structured semiconductor device including a package, interface substrate, controller and base die, and a plurality of cores all in a stacked configuration and transmit signals through a plurality of through silicon vias.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181
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