DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 05/20/2026 with respect to the objections and the 35 U.S.C. 112(b) rejections have been fully considered and are persuasive. They have been withdrawn.
Applicant’s arguments with respect to the 35 U.S.C. 102 and 103 rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 9, 12, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Ivanchenko et al (US20210382536)
Per claim 1, Ivanchenko teaches
(Original) An integrated circuit (IC) device comprising: a root domain comprising a logic circuit, a fault-structure circuit, a power delivery network (PDN) and a clock distribution network (CDN); and
(FIG. 1, [0020] the root domain is the monitoring circuit 210, [0021] “The monitoring circuit 210 can be configured to monitor for and detect failures of one or more other clusters of the same controller chip 100.” This teaches the fault-structure circuit in the root domain (which includes a logic circuit). [0035] the root domain can contain clock devices that offer clock signals for the cluster as well as a [0036] separate power supply)
a first branch domain comprising a logic circuit, a fault-structure circuit, a PDN, and a CDN, wherein:
(FIG. 1, [0022] the first branch domain is the voltage monitors 210a. It comprises its own power supply inputs 140a and monitors the power supply of clusters 110a. “The first cluster 110a and the cluster 110b may send signals indicating the status of various components. In some cases, the clusters may send alarm signals indicating a failure(s) with one or more components.” This teaches the fault-structure circuit within the first branch domain. “The clock tree 170a, 170b may produce or generate one or more clock signals for the controller units 120a, 120b or other components/devices of the same cluster.” This teaches that the first branch has a separate clock distribution network than that of the root domain)
the PDN of the first branch domain is operable independently of the PDN of the root domain; ([0034] the root domain is powered separately and independently than that of the branch domain)
the CDN of the first branch domain is operable independently of the CDN of the root domain; ([0015] a separate clock tree is used to generate one or more clock signals for the individual monitored clusters)
the fault-structure circuit of the first branch domain is configured to:
detect a hardware fault occurrence in the first branch domain; ([0022] the monitoring cluster (i.e., the first branch domain) detects a power supply input error, which may characterize a hardware fault)
determine a response to the detected hardware fault occurrence; and ([0022] the voltage monitor 210a (i.e., the first branch monitor) inform, by sending a signal regarding the hardware fault occurrence)
escalate the detected hardware fault occurrence to the fault- structure circuit of the root domain in accordance with the determined response; and ([0022] the voltage monitor 210a (i.e., the first branch monitor) inform the monitoring circuit (i.e., the root domain))
the fault-structure circuit of the root domain is configured to resolve the detected hardware fault occurrence escalated from the first branch domain. ([0025] the monitoring circuit 210 (i.e., the root domain) sends a signal to at least one other cluster indicating actions for the non-failing cluster to take, [0026]-[0027] this may look like the functioning cluster taking over the workload of the non-functioning cluster. Since such action is taken as “a remedial actions to accommodate or address the deficiencies of the failing cluster” [0026], it is considered “[resolving] the detected hardware fault occurrence” from the claim limitation)
Per claim 4, Ivanchenko teaches
(Currently amended) The device of claim 1, wherein the hardware fault occurrence is characterized as one of a lockstep fail, a clock fail, or an interconnect fail.
([0023] the failure can be a clock fail)
Per claim 5, Ivanchenko teaches
(Original) The device of claim 1, wherein the logic circuit of the first branch domain comprises one or more processors.
([0013] each cluster has one or more processors)
Per claim 9, Ivanchenko teaches
(Original) The device of claim 1, further comprising a set of one or more additional branch domains, wherein:
each additional branch domain comprises a logic circuit, a fault-structure circuit, a PDN, and a CDN;
(FIG. 1, [0022] the additional branch domain is taught by the voltage domain 210b. It comprises its own power supply inputs 140b and is used to monitor the power supply of cluster 110b. “The first cluster 110a and the cluster 110b may send signals indicating the status of various components. In some cases, the clusters may send alarm signals indicating a failure(s) with one or more components.” This teaches the fault-structure circuit within the first branch domain. “The clock tree 170a, 170b may produce or generate one or more clock signals for the controller units 120a, 120b or other components/devices of the same cluster.” This teaches that the first branch has a separate clock distribution network than that of the root domain)
the PDN of each additional branch domain is operable independently of the PDNs of the root domain, the first branch domain, and the other additional branch domains; ([0034] the root domain is powered separately and independently than that of the branch domain)
the CDN of each additional branch domain is operable independently of the CDNs of the root domain, the first branch domain, and the other additional branch domains; ([0015] a separate clock tree is used to generate one or more clock signals for the individual monitored clusters)
the fault-structure circuit of each additional branch domain is configured to:
detect a hardware fault occurrence in the additional branch domain; ([0022] the monitoring cluster (i.e., the first branch domain) detects a power supply input error, which may characterize a hardware fault)
determine a response to the detected hardware fault occurrence; and ([0022] the voltage monitor 210a (i.e., the first branch monitor) inform, by sending a signal regarding the hardware fault occurrence)
escalate the detected hardware fault occurrence to the fault-structure circuit of the root domain in accordance with the determined response; and ([0022] the voltage monitor 210a (i.e., the first branch monitor) inform the monitoring circuit (i.e., the root domain))
the fault-structure circuit of the root domain is configured to resolve the detected hardware fault occurrence escalated from the additional branch domain.
([0025] the monitoring circuit 210 (i.e., the root domain) sends a signal to at least one other cluster indicating actions for the non-failing cluster to take, [0026]-[0027] this may look like the functioning cluster taking over the workload of the non-functioning cluster. Since such action is taken as “a remedial actions to accommodate or address the deficiencies of the failing cluster” [0026], it is considered “[resolving] the detected hardware fault occurrence” from the claim limitation)
Per claim 12, Ivanchenko teaches
(Original) The device of claim 1, wherein the resolving by the root domain comprises rebooting the first branch domain without rebooting the device.
([0027] when a monitoring component, receives an error from the cluster, it identifies the failing cluster and may reset the cluster because [0017] each cluster is separated or electrically isolated from each other, resetting of one cluster will not affect the other clusters)
Per claim 17, it recites similar claim language as claim 1 and is rejected for similar reasons.
Per claim 20, it recites similar claim language as claim 1. It additionally recites:
a non-transient computer-readable medium comprising [executable] instructions ([0013]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko.
Per claim 2, Ivanchenko fails to teach explicitly:
(Currently amended) The device of claim 1, wherein:
a domain resiliency is resiliency to random hardware failures;
the root domain is characterized by a root resiliency;
the first branch domain is characterized by a first-branch resiliency; and
the root resiliency is greater than the first-branch resiliency.
However, it is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to understand that a resiliency exists for each domain and for the root resiliency to be greater than the first branch resilience. This would have been obvious because (1) in FIG. 1 there are potentially more hardware components that may cause an error in cluster A – i.e, the branch domain – as opposed to the monitoring cluster 200, and (2) the root domain operates independently and separately from the branch domain due to its separate PDN ([0034]) and separate CDN ([0022]), the root domain is able to remain operational even when the branch domain may be experiencing an error from a hardware failure.
Per claim 3, Ivanchenko teaches
(Currently amended) The device of claim 2, wherein:
the domain resiliency is inversely correlated to an area of the corresponding domain; (The domain resiliency, which have been previously established as representing the resilience against random hardware failure, is inversely correlated to the area of the corresponding domain. [0023] Since each component in the cluster may be a cause of an error, more components would mean more opportunities for failure. Since having more components in the cluster (i.e., a higher area of the corresponding domain) may increase the occurrence of random hardware failure, having a higher area of a corresponding domain is inversely correlated to the domain resiliency)
the root domain is characterized by an area;
(FIG. 1, [0022] the root domain is represented by “the monitoring circuit 210” and it has various components. The components take up space and thus characterize an area)
the first branch domain is characterized by an area; and
(FIG. 1, [0013] each cluster can contain one or more controller units or processing cores, a clock tree, or clock device, and various other components. Since these components take up space, the indication of the number of components may be characterize the area of the cluster)
the area of the root domain is smaller than the area of the first branch domain.
(In FIG. 1, there are potentially more hardware components that may potentially cause an error in the cluster A as opposed to the monitoring cluster 200, the monitoring cluster has a smaller area and has a higher domain resiliency)
Claims 6, 10, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Yu (US 20250094175 A1).
Per claim 6, Ivanchenko teaches
(Currently amended) The device of claim 1, wherein:
the logic circuit of the first branch domain comprises a plurality of processors;
the hardware fault occurrence is associated with only one failed processor of the plurality of processors; and
the resolving by the root domain …
([0013] each cluster has one or more processors; [0027] when an error is found the monitoring component repairs the failed cluster)
Ivanchenko fails to teach
comprises rebooting the one failed processor of the plurality of processors without rebooting the other processors of the plurality of processors.
However, Yu teaches
comprises rebooting the one failed processor of the plurality of processors without rebooting the other processors of the plurality of processors.
([0035] functional components may include various processors such as GPU component and ISP component. The functional component is isolated so that error correction -- which includes rebooting the functional component -- can be done without affecting operations to other components)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because by isolating the component, the invention increases the availability of the system (Yu, [0035]).
Per claim 10, Ivanchenko teaches
(Original) The device of claim 1, wherein:
the logic circuit of the first branch domain comprises a plurality of modules;
the hardware fault occurrence is in one module of the plurality of modules; and
the resolving by the root domain ...
([0013] each cluster has one or more modules; [0027] when an error is found the monitoring component repairs the failed cluster)
Ivanchenko fails to teach
comprises resetting the one module of the plurality of modules without resetting the other modules of the plurality of modules
However, Yu teaches
comprises resetting the one module of the plurality of modules without resetting the other modules of the plurality of modules ([0035] functional components may include various processors such as GPU component and ISP component. The functional component is isolated so that error correction -- which includes rebooting the functional component -- can be done without affecting operations to other components)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because by isolating the component, the invention increases the availability of the system (Yu, [0035]).
Per claim 18, it recites similar claim language as claim 10 and is rejected for similar reasons.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Moyer ("Chapter 1 - Introduction and Roadmap," Real World Multicore Embedded Systems, Newnes, 2013, Pages 1-10, ISBN 9780124160187).
Per claim 7, Ivanchenko fails to teach
(Original) The device of claim 1, wherein the logic circuit of the first branch domain comprises a hardware accelerator circuit.
However, Moyer teaches hardware accelerator circuit as a component in the system-on-chip (page 8, top of the page, "hardware acclerators")
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because the hardware accelerators -- when embedded into the multicore system -- can increase the performance of some computer-intensive function "dramatically" (Moyer, page 8, top of the page)
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Nguyen (US 7055060 B2).
Per claim 8, Ivanchenko fails to teach
(Original) The device of claim 1, wherein the device is configured to operate in a lockstep asymmetric mode wherein: the root domain operates with lockstep monitoring; and the first branch domain operates without lockstep monitoring.
However, Nguyen teaches the execution cores executing independently without the lockstep monitoring (col 4 lines 20-34, the two execution cores 120(a) and 120(b) execute independently and separately from one another without lockstep monitoring when executed under multi-core mode) and execution cores executing with lockstep monitoring (col 3 line 39-40 and col 1 line 31-42).
Because lockstep monitoring provides additional fault detection by comparing redundant circuitry, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to extend such monitoring to the monitoring circuit of Ivanchenko whose failure could affect system-level error handling, since "errors attributable to interrupt controllers 370 may still arise" (Nguyen, col 6 lines 10-13). Meanwhile, because the clusters operate separately and independently from the monitoring cluster 200 (Ivanchenko [0034]-[0035]), lockstep asymmetric mode operation without lockstep monitoring can be realized for separate clusters, which would provide the expected benefit for the monitoring cluster without requiring redundant execution or hardware for the separate clusters.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Zhou et al (US20240241778) in further view of Schultz et al (US20030074601)
Per claim 11, Ivanchenko teaches
(Original) The device of claim 1, wherein:
the first branch domain further comprises a memory comprising elements;
the hardware fault occurrence is in an element of the memory, wherein the hardware fault occurrence corresponds to a program using the element of the memory; and
the resolving by the root domain …
([0012]-[0013] the cluster has a memory device that could be configured to execute software; [0027] when an error is found in one of the clusters, the monitoring component repairs the failed cluster)
Ivanchenko fails to teach
comprises resetting the program without resetting the first branch domain.
However, Zhou teaches
comprises [localized response to fix the error of the memory device] without resetting the first branch domain.
(identifying and localizing specific hardware element in response to the uncorrectable error detected in the memory system, using localized corrective actions such as page offlining of the specific hardware element [0165]-[0166])
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Ivanchenko with the teaching of Zhou to teach that when a hardware failure specific within a memory device is detected, the exact source is identified to fix the issue without affecting the overall system (Zhou, [0165]-[0166]) because it would have the predictable benefit of increasing the availability of the overall system.
Ivanchenko in view of Zhou fails to teach
Resetting the program
However, Schultz teaches
Resetting the program ([0198] “[if the error is fixed], the thread can be restarted from the offending point onwards”)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Ivanchenko in view of Zhou – which teaches that a localized response like offlining affected pages can be used to fix error within the memory device – with the teaching of Schultz – which teaches that once the memory device’s error has been fixed, the thread can be restart from that section, because by doing so, it would predictability allow the software to resume operation using functional memory while avoiding the offline pages. Since individual thread is affected, the entire branch domain is not reset (Schultz, [0198]-[0199]).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Thevar et al (US 9766676 B2)
Per claim 13,
Ivanchenko fails to teach
(Original) The device of claim 12, wherein the rebooting comprises power cycling the first branch domain using at least one of the PDN of the first branch domain and the CDN of the first branch domain.
However, Thevar teaches
(Original) The device of claim 12, wherein the rebooting comprises power cycling the first branch domain using at least one of the PDN of the first branch domain and the CDN of the first branch domain.
(col 9 lines 36-46, when error is detected, the faulty domain is power cycled by ceasing the electric power and then resuming it)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because power cycling is one implementation method of rebooting.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Zhang ("Chapter 5 - Microprocessors," Advanced Industrial Control Technology, William Andrew Publishing, 2010, Pages 155-214, ISBN 9781437778076).
Per claim 14, Ivanchenko teaches
(Original) The device of claim 1, wherein:
the device is a system on chip; ([0011] the controller chip may be a system-on-chip device.)
Ivanchenko fails to teach
the device further comprises a network on chip (NoC); and
the root domain and first branch are interconnected by the NoC.
However, Zhang teaches
the device further comprises a network on chip (NoC); and
the root domain and first branch are interconnected by the NoC.
(page 202, bottom of the page: network-on-chip is used as a way to enable the integration of "high number of computational and storage blocks in a single chip")
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art in order to teach the use of NoC because it allows the components on the system-of-chip to communicate with each other (Zhang, page 202, bottom of the page).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Shacham et al (US 9442793 B2).
Per claim 15,
Ivanchenko fails to teach
(Original) The device of claim 1, wherein:
the first branch domain further comprises an alarm register;
the response to the detected hardware fault occurrence includes setting an alarm flag in the alarm register; and
the resolving by the root domain comprises clearing the alarm flag in the alarm register.
Shacham teaches
…an alarm register (col 1 line 45-50, “an error register”)
The response to the detected hardware fault occurrence includes setting an alarm flag in the alarm register; and (col 1 lines 45-50, “sets an error register upon detection of an error condition in the processing of tasks”)
The resolving… comprises clearing the alarm flag in the alarm register (col 2 line 33-35: “clearing the error register upon completion of error handling”)
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because by using the registers the controller of the cluster is able to keep track of its error condition (Shacham, col 2 lines 25-42).
Claims 16, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ivanchenko in view of Kim et al (US20220283888).
Per claim 16,
Ivanchenko fails to teach
(Original) The device of claim 1, wherein:
the first branch domain further comprises a watchdog timer;
the response to the detected hardware fault occurrence includes setting the watchdog timer; and
the fault-structure circuit of the first branch domain is configured to escalate the detected hardware fault occurrence to the fault-structure circuit of the root domain in response to an expiry of the watchdog timer.
However, Kim teaches when an error is detected, a timer is set, and when the error information is not initialized in the register during a predefined period of time, the system determines that the error occurred in the interrupt controller, and the error information specifying that the error has occurred in the interrupt controller is set up to the error detection unit ([0051]).
It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the prior art because otherwise the error information won't escalate properly to the error detection unit in the case the interrupt controller has an error ([0051]).
Per claim 19, it recites similar claim language as claim 16 and is rejected for similar reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pellegrini et al (“The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC,” arm, White Paper, 2020) (Year: 2020) teaches the system-on-chip architecture and the components.
Hannah (“Designing industrial controls for Industry 4.0 with Sitara AM6x processors,” Texas Instruments, 2018) (Year: 2018) teaches the system-on-chip architecture and the components.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST.
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/K.L.R./ Examiner, Art Unit 2114
/JOSEPH O SCHELL/Primary Examiner, Art Unit 2114
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