Prosecution Insights
Last updated: October 02, 2026
Application No. 19/058,334

SEMICONDUCTOR DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

Non-Final OA §102§103
Filed
Feb 20, 2025
Priority
Apr 01, 2024 — JP 2024-058895
Examiner
LE, CHAU D
Art Unit
Tech Center
Assignee
Sharp Semiconductor Innovation Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
461 granted / 541 resolved
+25.2% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
17 currently pending
Career history
557
Total Applications
across all art units

Statute-Specific Performance

§101
15.6%
-24.4% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
15.1%
-24.9% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-7 are pending. Information Disclosure Statement The information disclosure statement (IDS) submitted on 2/20/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 3-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Landry et al. (US Pub No 2022/0414268). Prior art Landry teaches Claim: 1. A semiconductor device comprising: a dividing section configured to divide data into two or more pieces of divisional data (e.g., “When encrypting using a block algorithm, the data to be encrypted is divided into blocks of bits of the same size, such as blocks of 128 bits for AES or SM” ¶ 0026); a block encryption executing section configured to apply, to only one or some of the two or more pieces of divisional data, a specific process included in a block encryption algorithm (e.g., “masking the data to be encrypted by adding or multiplying it with random data (a mask), for example, generated by the random number generator 16. Thus, the data is never handled by the encryption algorithm alone” ¶ 0028 teaches applying a masking to the data before an encryption algorithm ¶ 0033); and a data retaining section configured to retain, in respective blocks, the two or more pieces of divisional data to only one or some of which the specific process has been applied, so that pieces of side-channel information radiated differ from each other between at least some of the blocks (e.g., preventing side-channel attacks ¶ 0027-0028 by applying different cryptographic operations using masks data ¶ 0071-0078). Prior art a Landry further teaches Claim: 3. The semiconductor device as set forth in claim 1, wherein the dividing section performs a process for assigning, according to a value of random number which has been generated for each predetermined information amount of the data, each bit string which has the predetermined information amount and which is included in the data to any one piece of the two or more pieces of divisional data (e.g., “A countermeasure to this type of attack may include masking the data to be encrypted by adding or multiplying it with random data (a mask), for example, generated by the random number generator 16” ¶ 0028 using random value ¶ 0033, 0036 & 0132). Prior art a Landry further teaches Claim: 4. The semiconductor device as set forth in claim 1, wherein: the dividing section divides the data into three or more pieces of divisional data; and the data retaining section retains, in respective blocks, the three or more pieces of divisional data so that pieces of the side-channel information radiated differ from one another among all of the blocks (e.g., divides the data into a plurality of pieces teaches at least three or more ¶ 0026 & 0086). Prior art a Landry further teaches Claim: 5. The semiconductor device as set forth in claim 1, wherein: the block encryption algorithm is Advanced Encryption Standard (AES); and the specific process includes an AddRoundKey process (e.g., AES ¶ 0080-0084). Prior art a Landry further teaches Claim: Claims 6-7 are substantially similar to claim 1 above disclosing a method and non-transitory medium, respectively, and therefore the claim is likewise rejected. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Landry et al. (US Pub No 2022/0414268) in view of Johnson et al. (US Pub No 2018/0091296). With respect to claim 2, Landry discloses the claimed subject matter as discussed above with dividing data into a plurality of blocks (¶ 0026 & 0086), but does not explicitly discloses wherein the dividing section divides the data into the two or more pieces of divisional data such that at least any two pieces of the two or more pieces of divisional data differ from each other in information amount. However, analogous art from the same field of endeavor, Johnson teaches this with “using any standard technique for adapting a block cipher to process data of different sizes” in order to protect against side-channel attacks (¶ 0140). Therefore, based on Landry in view of Johnson, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Johnson to the system of Landry in order to “desirable to be able to provide similar cipher-like functionality in a manner that uses only a small number of hardware or software resources” (¶ 0003-0004) . Hence, it would have been obvious to combine the references to obtain the invention as specified in the instant claim. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAU LE whose telephone number is (571)270-7217. The examiner can normally be reached M-F 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINGLAN EDWARDS can be reached at (571) 270-5440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHAU LE/Primary Examiner, Art Unit 2408
Read full office action

Prosecution Timeline

Feb 20, 2025
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+16.9%)
2y 9m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allowance rate.

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