DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the communication filed on 2/20/2025.
Claims 1-24 are pending.
Examiner’s notes:
Claims 13-22 recite statutory subject matter under 35 U.S.C. 101 as a machine including hardware ([0015], an ingress arbiter is read as an enqueuing/dequeuing ingress processor, fig. 1, further including a memory and a buffer).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-12, 22-24 is/are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Peled et al. (US 9,892,083).
For claim 22, Peled discloses a network switching system, comprising:
an ingress arbiter that is configured to define a memory space that is divided into a packet buffer and an accelerated memory (fig. 1, packet processing module 108, col. 3, l. 47-53, memory 116 such as RAM and cache 112 such as L1, L2 (on processor) cache inherently smaller and faster than RAM));
a packet memory buffer manager configured to write and read from the packet buffer (fig. 1, arrows 3, 4, packet processing module with rate limiter for writing to and reading from the memory or packet buffer);
wherein the ingress arbiter is configured to determine one or more congestion levels associated with ingress network traffic; and, upon enqueuing incoming packets, select one or more memory locations in the memory space for storing portions of each of the incoming packets based on at least one of the determined congestion levels (col. 6, l. 17-57, storing ingress packets or portions thereof in the memory or the cache depending on a congestion level).
For claim 23, Peled discloses the one or more selected memory locations includes a memory location in the accelerated memory for storing a start-of-packet (SOP) portion of an incoming packet in response to determining that the at least one of the determined congestion levels is below a congestion level threshold (col. 6, l. 17-57, storing packets or headers in a cache when there is no congestion).
For claim 24, Peled discloses the one or more selected memory locations includes a memory location in the packet buffer for storing a start-of-packet (SOP) portion of an incoming packet in response to determining that the at least one of the determined congestion levels reaches or exceeds a congestion level threshold (col. 6, l. 17-57, col. 5, l. 39-52, storing packets or headers in a memory/buffer when there is congestion).
Claims 10-12 recite a method implemented by the system of claims 22-24 and are thus rejected for the same rationale in claims 22-24.
Reasons for Allowance
The following is an examiner's statement of reasons for allowance:
Claims 1-9, 13-21 are allowed.
By interpreting the claims in light of the Specification (fig. 3B and associated Specification), the Examiner finds the claimed invention to be patentably distinct from the prior art of records.
Peled et al. (US 9,892,083) discloses a network switching system, comprising:
an ingress arbiter (fig. 1, packet processing module 108) configured to allocate in a memory space a packet buffer of a first size and having a first memory access latency and an accelerated memory of a second size that is smaller than the first size and having a second memory access latency that is smaller than the first memory access latency (fig. 1, col. 3, l. 47-53, memory 116 such as RAM and cache 112 such as L1, L2 (on processor) cache inherently smaller and faster than RAM);
a packet memory buffer manager configured to write and read from the packet buffer (fig. 1, arrows 3, 4, packet processing module with rate limiter for writing to and reading from the memory or packet buffer);
in response to determining that the congestion measure is below a congestion threshold, the ingress arbiter is configured to enqueue an ingress packet by storing a start-of-packet (SOP) portion of the ingress packet in the accelerated memory (col. 6, l. 17-57).
Peled discloses storing only a SOP of a packet in the cache or storing entire packet in the cache depending on packet classification (col. 6, last 2 pars).
Petersen (US 2010/0316052) discloses header cache and data cache ([0024]).
Wei et al. (US 2022/0321492) discloses receiving a first packet, and identifying a queue number of the first packet, where the queue number indicates a queue for storing the first packet; querying a queue latency based on the queue number; determining a first latency threshold based on usage of the first storage medium; and buffering the first packet in the first storage medium or the second storage medium based on the queue latency and the first latency threshold (abstract).
The prior arts do not render obvious “in response to determining that the congestion measure is below a congestion threshold, the ingress arbiter is configured to enqueue an ingress packet by storing a start-of-packet (SOP) portion of the ingress packet in the accelerated memory; storing one or more non-SOP portions of the ingress packet in the packet buffer; and wherein, in response to determining that the congestion measure is not below the congestion threshold, the ingress arbiter is configured to enqueue the ingress packet by storing all portions of the ingress packet in the packet buffer”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is included in form PTO 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU T HOANG whose telephone number is (571) 270-1253. The examiner can normally be reached Mon-Fri 9 AM -5 PM.
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/HIEU T HOANG/Primary Examiner, Art Unit 2449
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