Prosecution Insights
Last updated: October 01, 2026
Application No. 19/058,389

LIQUID CRYSTAL DISPLAY DEVICE HAVING IMPROVED ELECTROSTATIC DISCHARGE RESISTANCE

Non-Final OA §DP
Filed
Feb 20, 2025
Priority
Dec 27, 2006 — JP 2006-352377 +6 more
Examiner
RAABE, CHRISTOPHER M
Art Unit
Tech Center
Assignee
Magnolia White Corporation
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
566 granted / 829 resolved
+8.3% vs TC avg
Strong +27% interview lift
Without
With
+27.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
26 currently pending
Career history
843
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
59.4%
+19.4% vs TC avg
§102
33.1%
-6.9% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 829 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-19 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12253770. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent anticipate those of the instant application (see below). Application 19/058389 USPN 12253770 1. A display device comprising: a first insulating layer including pixel electrodes and a common electrode in a pixel area and including a peripheral circuit and a dummy wiring in a peripheral area; a second insulating layer including a conductive film provided at an opposite side of the second insulating layer to the first insulating layer side, the conductive film overlapping the pixel area, the peripheral area, and the dummy wiring in plan view; and a pixel layer between the first insulating layer and the second insulating layer, wherein the peripheral circuit includes a common wiring supplying a common electric potential to the common electrode, the common wiring being separated from the dummy wiring, the dummy wiring is located between the peripheral circuit and an outermost edge of the first insulating layer at the outermost edge of the first insulating layer, the dummy wiring is made of a metal layer along the pixel area and peripheral circuit on at least three sides of the first insulating layer and is connected to a reference potential outside the first insulating layer, and the dummy wiring is provided to discharge electric potential rise on the first insulating layer that occurs due to coupling with electric potential rise of the conductive film on the second insulating layer. 2. The display device according to claim 1, wherein the conductive film is maintained at a predetermined electric potential. 3. The display device according to claim 1, wherein the dummy wiring does not intersect with the periphery circuit. 4. The display device according to claim 1, wherein the dummy wiring is disposed along the outer periphery of the side of the first insulating layer and does not constitute a closed path, both ends of the dummy wiring are extended to a portion that connects with the external wiring and are connected to the reference potential of the external circuit through the external wiring. 5. The display device according to claim 1, wherein the reference potential outside the first insulating layer is separate from a reference potential of the display device. 6. The display device according to claim 1, wherein the dummy wiring has two ends, wherein each end is connected to the reference potential outside the first insulating layer. 7. The display device according to claim 1, wherein the dummy wiring is disposed along three sides of the first insulating layer and is disposed along at least a part of a fourth side. 8. The display device according to claim 1, wherein the dummy wiring is covered with a third insulating layer. 9. The display device according to claim 1, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlaps the seal member in plan view. 10. A display device comprising: a first insulating layer including pixel electrodes in a pixel area and including a peripheral circuit and a dummy wiring in a peripheral area; a second insulating layer including a conductive film provided at an opposite side of the second insulating layer to the first insulating layer side, the conductive film overlapping the pixel area, the peripheral area, and the dummy wiring in plan view; and a pixel layer between the first insulating layer and the second insulating layer, the dummy wiring is located between the peripheral circuit and an outermost edge of the first insulating layer at the outermost edge of the first insulating layer, the dummy wiring is made of a metal layer along the pixel area and peripheral circuit on at least three sides of the first insulating layer and is connected to a reference potential outside the first insulating layer, the dummy wiring is provided to discharge electric potential rise on the first insulating layer that occurs due to coupling with electric potential rise of the conductive film on the second insulating layer, the dummy wiring is covered with a third insulating layer. 11. The display device according to claim 10, wherein the pixel electrodes are located on the side of the pixel layer of a fourth insulating layer. 12. The display device according to claim 10, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlaps the seal member in plan view. 13. The display device according to claim 10, wherein the conductive film is maintained at a predetermined electric potential. 14. The display device according to claim 10, wherein the dummy wiring does not intersect with the periphery circuit. 15. The display device according to claim 10, wherein the dummy wiring is disposed along the outer periphery of the side of the first insulating layer and does not constitute a closed path, both ends of the dummy wiring are extended to a portion that connects with the external wiring and are connected to the reference potential of the external circuit through the external wiring. 16. The display device according to claim 10, wherein the reference potential outside the first insulating layer is separate from a reference potential of the display device. 17. The display device according to claim 10, wherein the dummy wiring has two ends, wherein each end is connected to the reference potential outside the first insulating layer. 18. The display device according to claim 10, wherein the dummy wiring is disposed along three sides of the first insulating layer and is disposed along at least a part of a fourth side. 19. The display device according to claim 10, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlaps the seal member in plan view. 1. A display device comprising: a first insulating layer including pixel electrodes and a common electrode in a pixel area and including a peripheral circuit and a dummy wiring in a peripheral area surrounding the pixel area; a second insulating layer including a conductive film provided at an opposite side of the second insulating layer to the first insulating layer side, the conductive film overlapping the pixel area, the peripheral area, and the dummy wiring in plan view; and a pixel layer between the first insulating layer and the second insulating layer, wherein the peripheral circuit includes a common wiring supplying a common electric potential to the common electrode, the common wiring being separated from the dummy wiring, the dummy wiring is located between the peripheral circuit and an outermost edge of the first insulating layer at the outermost edge of the first insulating layer, the dummy wiring is made of a continuous metal layer surrounding the pixel area and peripheral circuit on at least three sides of the first insulating layer and is connected to a reference potential outside the first insulating layer, and the dummy wiring is provided to discharge electric potential rise on the first insulating layer that occurs due to coupling with electric potential rise of the conductive film on the second insulating layer. 2. The display device according to claim 1, wherein the conductive film is maintained at a predetermined electric potential. 3. The display device according to claim 1, wherein the dummy wiring does not intersect with the periphery circuit. 4. The display device according to claim 1, wherein the dummy wiring surrounds the outer periphery of the side of the first insulating layer and does not constitute a closed path, both ends of the dummy wiring are extended to a portion that connects with the external wiring and are connected to the reference potential of the external circuit through the external wiring. 5. The display device according to claim 1, wherein the reference potential outside the first insulating layer is separate from a reference potential of the display device. 6. The display device according to claim 1, wherein the dummy wiring has two ends, wherein each end is connected to the reference potential outside the first insulating layer. 7. The display device according to claim 1, wherein the dummy wiring surrounds three sides of the first insulating layer and surrounds at least a part of a fourth side. 8. The display device according to claim 1, wherein the dummy wiring is covered with a third insulating layer. 9. The display device according to claim 1, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlapping the seal member in plan view. 10. A display device comprising: a first insulating layer including pixel electrodes and a common electrode in a pixel area and including a peripheral circuit and a dummy wiring in a peripheral area surrounding the pixel area; a second insulating layer including a conductive film provided at an opposite side of the second insulating layer to the first insulating layer side, the conductive film overlapping the pixel area, the peripheral area, and the dummy wiring in plan view; and a pixel layer between the first insulating layer and the second insulating layer, wherein the peripheral circuit includes a common wiring supplying a common electric potential to the common electrode, the common wiring being separated from the dummy wiring, the dummy wiring is located between the peripheral circuit and an outermost edge of the first insulating layer at the outermost edge of the first insulating layer, the dummy wiring is made of a continuous metal layer surrounding the pixel area and peripheral circuit on at least three sides of the first insulating layer and is connected to a reference potential outside the first insulating layer, the dummy wiring is provided to discharge electric potential rise on the first insulating layer that occurs due to coupling with electric potential rise of the conductive film on the second insulating layer, the dummy wiring is covered with a third insulating layer, and the common electrode is located on the side of the pixel layer of the third insulating layer. 11. The display device according to claim 10, wherein the common electrode is covered with a fourth insulating layer. 12. The display device according to claim 11, wherein the pixel electrodes are located on the side of the pixel layer of the fourth insulating layer. 13. The display device according to claim 11, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlapping the seal member in plan view. 14. The display device according to claim 10, wherein the conductive film is maintained at a predetermined electric potential. 15. The display device according to claim 10, wherein the dummy wiring does not intersect with the periphery circuit. 16. The display device according to claim 10, wherein the dummy wiring surrounds the outer periphery of the side of the first insulating layer and does not constitute a closed path, both ends of the dummy wiring are extended to a portion that connects with the external wiring and are connected to the reference potential of the external circuit through the external wiring. 17. The display device according to claim 10, wherein the reference potential outside the first insulating layer is separate from a reference potential of the display device. 18. The display device according to claim 10, wherein the dummy wiring has two ends, wherein each end is connected to the reference potential outside the first insulating layer. 19. The display device according to claim 10, wherein the dummy wiring surrounds three sides of the first insulating layer and surrounds at least a part of a fourth side. 20. The display device according to claim 10, further comprising: a seal member provided between the first insulating layer and the second insulating layer to seal the pixel layer, wherein the dummy wiring overlapping the seal member in plan view. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. USPN 2006/0061268, 2008/0123032, 8830409. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher Raabe whose telephone number is (571)272-8434. The examiner can normally be reached M-F 0530-1430. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R Greece can be reached at (571)272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER M RAABE/Primary Examiner, Art Unit 2875
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Prosecution Timeline

Feb 20, 2025
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751186
DISPLAY PANEL
3y 0m to grant Granted Sep 29, 2026
Patent 12750929
DISPLAY DEVICE AND ELECTRONIC APPARATUS
3y 0m to grant Granted Sep 29, 2026
Patent 12740290
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE
3y 0m to grant Granted Sep 15, 2026
Patent 12740231
DISPLAY DEVICE
3y 1m to grant Granted Sep 15, 2026
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OPTICAL MEMBER AND DISPLAY APPARATUS COMPRISING THE SAME
3y 0m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
96%
With Interview (+27.3%)
2y 8m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 829 resolved cases by this examiner. Grant probability derived from career allowance rate.

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