DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continuity
Examiner notes this application claims continuity from parent 17/055,950.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/20/25; 6/3/25; 9/10/25; 12/31/25; and 9/9/26 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
A title such as the following is suggested: Slope Compensation Circuit for a Voltage Regulator.
Claim Objections
Claims 6-7 and 15-16 are objected to because of the following informalities:
in claim 6, line 3, “threshold detection circuit is configurable” should be ‘the threshold detection circuit is configurable’. Likewise for claim 15.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 requires the second comparator input is configurable to receive a voltage proportional to a difference between a reference voltage and a voltage at the output voltage terminal, but as shown in Applicant’s Figure 3, it is the first comparator input (Fig. 3 106 inverting input) which is configurable to receive a voltage (Fig. 3 VREF_INT) proportional to a difference between a reference voltage and a voltage at the output voltage terminal, while the second comparator input (Fig. 3 106 non-inverting input) is coupled to the slope compensation circuit (Fig. 3 350) as required by independent claim 1. The second claim is indefinite when interpreted in light of the specification because it is unclear whether Applicant references the first or the second comparator input because of the contradiction with independent claim 1 from which it depends. For the purpose of examination, the claim language of claim 2 shall be interpreted as the first comparator input is configurable to receive a voltage proportional to a difference between a reference voltage and a voltage at the output voltage terminal. Likewise for claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 8, 10, 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2017/0025947) in view of Pastore (US 2020/0119652).
With respect to claim 1, Wang discloses a circuit comprising: a comparator (Fig. 3 353) having first and second comparator inputs and a comparator output, in which the first comparator input (Fig. 3 353 non-inverting input) is coupled to a feedback terminal (Fig. 3 output terminal from error amplifier 351); a logic circuit (Fig. 3 354) having at least a first logic input, in which the first logic input (Fig. 3 input from 356) is coupled to the comparator output; a drive circuit (Fig. 3 301-306) having a drive input (Fig. 3 Φ), a sense terminal (Fig. 3 Vsens-dc) and a drive output (Fig. 3 Vout), in which the drive input is coupled (Fig. 3 Φ) to the logic output, and the drive output is coupled (Fig. 3 coupled through 353,354,303-303) to the feedback terminal; and a slope compensation circuit (Fig. 3 352) coupled between the second comparator input (Fig. 3 353 inverting input) and wherein the slope compensation circuit includes: a capacitor (Fig. 5B 521) coupled between the second comparator input (Fig. 5B RampOut is output to Fig. 3 353 inverting input) and a compensation terminal (Fig. 5B terminal 521-512); a resistor (Fig. 5B 512) coupled (Fig. 5B coupled through 503,504,510,511) between the compensation terminal (Fig. 5B terminal 521-512) and an output voltage terminal (Fig. 3 Vin is output voltage from output voltage terminal of Fig. 3 351); and a transistor (Fig. 5B 510) coupled (Fig. 5B coupled through 511) between the compensation terminal (Fig. 5B terminal 521-512) and a ground terminal (Fig. 5B ground symbol) and having a control terminal (Fig. 5B 510 gate) coupled (Fig. 5B coupled through 503-504) to the sense terminal (Fig. 5B Vsns-dc). Wang discloses wherein the control logic circuit has at least a first logic input from the comparator output (Fig. 3 353 output) and remains silent as to whether the control logic circuit utilizes a clock (i.e. whether 354 has an internal clock). It was well known before the effective filing date of the claimed invention to implement where converter control logic circuits are synchronous and receive a clock input.
Pastore discloses a logic circuit (Fig. 3 328) having first (Fig. 3 U/D) and second (Fig. 3 CLK) logic inputs and a logic output (Fig. 3 REQ), in which the first logic input is coupled to the comparator output (Fig. 3 327 output), and the second logic input is coupled to a clock terminal (Fig. 3 333). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a logic circuit having first and second logic inputs and a logic output, in which the first logic input is coupled to the comparator output, and the second logic input is coupled to a clock terminal in order to implement the desired switching frequency.
With respect to claim 3, Wang in view of Pastore make obvious the circuit of claim 1, wherein the capacitor is a first capacitor (Fig. 5B ) , and the circuit further comprises a second capacitor (Fig. 3 309) coupled (Fig. 3 coupled through 303,351 and 353) between the feedback terminal (Fig. 3 output of 353) and the output voltage terminal (Fig. 3 output of 351).
With respect to claim 4, Wang in view of Pastore make obvious the circuit of claim 3, further comprising an inductor (Fig. 3 301) coupled (Fig. 3 ) between the feedback terminal and the output voltage terminal.
With respect to claim 5, Wang in view of Pastore make obvious the circuit of claim 4, wherein the resistor is a first resistor (Fig. 5B 512), and the circuit further comprises: a third capacitor (Fig. 3 Co) coupled (Fig. 3 coupled throught 301,303) between the output voltage terminal and the ground terminal; and a second resistor (Fig. 5B 502) coupled (Fig. 5B coupled through 504,510) between the output voltage terminal and the ground terminal.
With respect to claim 8, Wang in view of Pastore make obvious the circuit of claim 1 as set forth above, and Wang does not require use of a state machine in the logic circuit. The use of state machines was well known before the effective filing date of the claimed invention. It
Pastore discloses wherein the logic circuit includes a state machine (Fig. 3 355) configurable to control (Fig. 3 REQ) turning the drive circuit on or off (Fig. 1B DR controlled by REQ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the logic circuit includes a state machine configurable to control turning the drive circuit on or off, in order to take advantage of the fast computation and low overhead of a state machine.
With respect to claim 10, Wang in view of Pastore make obvious an automotive power system [capable of intended use], comprising: a buck voltage converter (Wang paragraphs 2-3 and Pastore paragraph 66). While Wang does not require the use of a buck converter in the embodiment of Figure 3, the use of buck converters were well known before the effective filing date of the claimed the invention and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a buck converter in an automative power system in order to lower the desired output voltage from the available input voltage in an automotive power system. See claim 1 for additional details.
With respect to claims 12-14 and 17, Wang in view of Pastore make obvious the automotive power system as set forth above. See claims 3-5 and 8, respectively, for additional details.
Claim(s) 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2017/0025947) in view of Pastore (US 2020/0119652) and further in view of McJimsey (US 8,710,810).
With respect to claim 9, Wang in view of Pastore make obvious the circuit of claim 8 as set forth above, and remain silent as to implementing an edge detection circuit. The use of edge detection circuits were known before the effective filing date of the claimed invention.
McJimsey discloses wherein the logic circuit includes an edge detection circuit (Fig. 44 4304) having an edge detection input (Fig. 4 input from 4302) and an edge detection output (Fig. 44 output to 4312), wherein the edge detection input is coupled to the clock terminal (Fig 4 4302), and the edge detection output is coupled to the PWM logic. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the logic circuit includes an edge detection circuit having an edge detection input and an edge detection output, wherein the edge detection input is coupled to the clock terminal, and the edge detection output is coupled to the state machine, in order to accurately detect the clock edge.
With respect to claim 18, Wang in view of Pastore and McJimsey make obvious the automotive power system as set forth above. See claim 9 for additional details.
Double Patenting
Claims 1-2, 6, 8, 10-11, 15 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 10-12 and 14 of U.S. Patent No. 12,261,529. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present are application are a broadened version of the patent which anticipate the rejected claims and recites all features of the present application including the claimed comparator, logic circuit, drive circuit and slope compensation circuit. While claim 1 of the patent does not recite the claimed sense terminal, claim 1 of the patent requires the threshold detection circuit to have the claimed sense terminal, and claim 10 of the patent requires the control terminal of the third transistor to be coupled to the sense terminal. The limitation of claim 2 is anticipated by the claimed amplifier in claim 1 in the patent. The threshold detection circuit of claim 6 is anticipated by the threshold detection circuit of claim 1 of the patent. The state machine of Claim 8 is anticipated by the state machine of claim 7 of the patent. Although the patent does not claim a buck voltage converter in an automative power system, it was well known before the effective filing date of the claimed invention to implement buck converters in automative power systems and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed voltage converter as a buck voltage converter in an automotive power system, therefore claims 10-11, 15 and 17 are anticipated by claim 12 which depends from claims 1 and 11
Allowable Subject Matter
Claims 6 and 15 are rejected under obviousness type double patenting, but would be allowed upon receipt of an appropriate terminal disclaimer and if the claim objections stated above were overcome and if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a threshold detection circuit having a threshold detection input and a threshold detection output, wherein the threshold detection output is coupled to a third logic input, threshold detection circuit is configurable to sense a current flowing into the ground terminal and provide a threshold signal at the threshold detection output responsive to the sensed current crossing a current threshold.
Claim 15 is indicated as possessing indicated allowable subject matter primarily for the same reasons as claim 6 above.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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