DETAILED ACTION
Re Application No. 19/058527, this action responds to the arguments dated 06/23/2026.
Claims 1-20 are pending. No claims have been amended.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Re claims 10-16, Applicant argues that Examiner’s rejection under 35 USC § 112(b) was improper, as the claimed subject matter is described in at least one of the drawings. In response, Applicant’s first argument has been fully considered, and is deemed persuasive. Accordingly, Examiner’s rejections under 35 USC § 112(b) have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Linkovsky et al (US 2018/0314421 A1) in view of Muthiah (S 2022/0083256 A1).
Re claim 1, Linkovsky discloses the following:
A method, comprising: providing, by a memory sub-system, a storage space accessible to a host system via entering requests in a plurality of submission queues (Fig. 3; ¶ 51). The host system enters commands (requests) into multiple submission queues;
providing, by the memory sub-system, a memory space accessible to the host system (¶ 89). The storage devices provide a logical address space (memory space) accessible to the host system;
identifying, by the memory sub-system, a batch of first requests [of] the submission queues; and (Abstract). The memory device (sub-system) identifies read or write streams (a batch of first requests) of multiple submission queues;
determining, by the memory subsystem, a memory allocation scheme configured to identify, in the memory space, placements of memory blocks to be allocated for the first requests (¶ 20). For the identified read or write streams, the memory device determines the placement of the individual commands within the logical block address range (placements of memory blocks to be allocated for the first requests).
Muthiah discloses identifying, by the memory subsystem, a batch of first requests pending in the submission queue[…] (¶ 36) The storage device utilizes metadata associated with commands pending in a submission queue in order to identify a sequential group of commands (batch of first requests) that are pending in a submission queue.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the sequential command detection of Linkovsky to utilize metadata to detect sequential commands while still pending in the submission queue(s), as in Muthiah, because Muthiah suggests that detecting sequential commands pending in submission queues would enable prefetching to be adjusted in order to save time and resources (¶ 36).
Re claim 2, Linkovsky and Muthiah disclose the method of claim 1, and Linkovsky further discloses the following:
wherein the method further comprises executing, after the memory allocation scheme is determined, the first requests (¶ 24-25). The memory allocation scheme of the detected stream commands is used to subsequently execute those commands;
wherein the determining of the memory allocation scheme includes: aggregating the memory blocks according to size for placement in contiguous regions in the memory space (¶ 20 and 66). The commands in the stream command (memory allocation scheme) may be analyzed for logical block address and size (¶ 20), for placement in contiguous LBAs (¶ 66).
Re claim 17, Linkovsky discloses the following:
A non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising: (¶ 28);
identifying a batch of first requests [of] a plurality of submission queues; and (Abstract). The memory device (sub-system) identifies read or write streams (a batch of first requests) of multiple submission queues;
determining a memory allocation scheme configured to identify, in a memory space of a memory sub-system, placements of memory blocks to be allocated for the first requests (¶ 20 and 89). For the identified read or write streams, the memory device determines the placement of the individual commands within the logical block address range (placements of memory blocks to be allocated for the first requests) (¶ 20). The logical block address range is a memory space (¶ 89).
Muthiah discloses identifying a batch of first requests pending in the submission queue[…] (¶ 36) The storage device utilizes metadata associated with commands pending in a submission queue in order to identify a sequential group of commands (batch of first requests) that are pending in a submission queue.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the sequential command detection of Linkovsky to utilize metadata to detect sequential commands while still pending in the submission queue(s), as in Muthiah, because Muthiah suggests that detecting sequential commands pending in submission queues would enable prefetching to be adjusted in order to save time and resources (¶ 36).
Claims 3-9 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Linkovsky in view of Muthiah, further in view of B N et al (US 11599298 B1).
Re claim 3, Linkovsky and Muthiah disclose the method of claim 2, but do not specifically disclose estimating times to free the memory blocks.
B N et al discloses that determining of the memory allocation scheme includes: estimating times to free the memory blocks to determine the placements of the memory blocks relative to each other in the memory space (Fig. 4 and associated text). The pre-erasing system estimates an appropriate time to free the memory blocks in order to present an ordered placement of blocks relative to each other in the memory space, such that when a predicted sequential write is received, the blocks in the sequential order are ready for programming. Additionally, timestamps for erased blocks are compared to a threshold in order to estimate whether the blocks may be corrupted and must be re-erased.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the sequential command processing of Linkovsky (combined with Muthiah) to predict appropriate times to free memory blocks for placement for sequential write commands, as in B N, because B N suggests that pre-erasing at a predicted appropriate time improves performance (Abstract).
Re claim 4, Linkovsky, Muthiah, and B N disclose the method of claim 3, and B N further discloses that the estimating is based on hints provided by the host system in the first requests (Fig. 4, step 430). The sequential command prediction, which is used to estimate when to erase blocks, is based on hints from the host such as LBA, length, and timestamp/frequency of writes.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Linkovsky, Muthiah, and B N, for the reasons noted in claim 3 above.
Re claim 5, Linkovsky, Muthiah, and B N disclose the method of claim 3, and Linkovsky further discloses submission queues (¶ 51).
B N further disclose the method of claim 3, and B N further discloses that the estimation is based on identifications of submission queue[…] from which the first requests are received (Fig. 5, CMDQ Predict Block Full, and associated text). The system may also determine an appropriate time to erase blocks based on a count (identification) of a number of requests in a command queue (submission queue).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Linkovsky, Muthiah, and B N, for the reasons noted in claim 3 above.
Re claim 6, Linkovsky, Muthiah, and B N disclose the method of claim 3, and Linkovsky further discloses determining an execution schedule for the first requests during the determining of the memory allocation scheme (¶ 71). The stream detection manager detects whether commands are in a particular order. If they are ordered, as in a stream command, they may be accumulated into an ordered entry, while if they are out-of-order commands, they are executed out-of-order.
Re claim 7, Linkovsky, Muthiah, and B N disclose the method of claim 6, and Linkovsky further discloses that the execution schedule is configured to select one or more of the first requests for out-of-order execution (¶ 71).
Re claim 8, Linkovsky, Muthiah, and B N disclose the method of claim 7, and Linkovsky further discloses that the plurality of submission queues are configured according to a standard for non-volatile memory express (NVMe) (¶ 47). The submission queues are configured according toe the NVMe standard.
Re claim 9, Linkovsky, Muthiah, and B N disclose the method of claim 8, and Linkovsky further discloses that the plurality of submission queues are configured in the memory sub-system (Fig. 3). The submission queues are part of the host memory (memory subsystem).
Re claim 18, Linkovsky, Muthiah, and B N disclose the method of claim 3 (including limitations of parent claims 1 and 2); accordingly, they also disclose a computer storage medium storing instructions implementing that method, as in claim 18 (see Linkovsky ¶ 28).
Re claim 19, Linkovsky, Muthiah, and B N disclose the computer storage medium of claim 18, and Linkovsky further discloses the following:
determining an execution schedule for the first requests during the determining of the memory allocation scheme (¶ 71). See claim 6 above;
wherein the execution schedule is configured to select one or more of the first requests for out of order execution (¶ 71). See claim 7 above;
B N further discloses that the times to free the memory blocks are based at least in part on the execution schedule (Fig. 4 and associated text). The predicted appropriate erase (free) times are based on the schedule of commands that are predicted to execute (execution schedule).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Linkovsky, Muthiah, and B N, for the reasons noted in claim 3 above.
Re claim 20, Linkovsky, Muthiah, and B N disclose the computer storage medium of claim 19, and Linkovsky further discloses that the plurality of submission queues are configured according to a standard for non-volatile memory express (NVMe) (¶ 47). See claim 8 above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2013/0086309 A1) in view of Muthiah, further in view of Linkovsky, and further in view of Alexander Gillis, DRAM (dynamic random access memory), published 03/18/2024, available at https://www.techtarget.com/it-infrastructure/definition/DRAM-dynamic-random-access-memory, last accessed 09/10/2026 [hereinafter “Gillis”].
Re claim 10, Lee discloses the following:
A memory sub-system, comprising: first memory […] configured to provide a storage space accessible to a host system (Fig. 8A; ¶ 91-92 and 106). The memory subsystem comprises a flash module associated with a respective address space (storage space) (¶ 106). The memories communicate with a host system (¶ 91-92);
second memory […] configured to provide a memory space accessible to the host system; and (Fig. 8A; ¶ 91-92 and 106). The memory subsystem also comprises a DRAM module associated with a respective address space (memory space) (¶ 106). The memories communicate with a host system (¶ 91-92);
and a controller configured to (Fig. 3A, controller 306).
Muthiah discloses the following:
first memory cells configured to provide a storage space (Fig. 1, NVM 110, memory cells 116). The NVM (storage space) is provided by memory cells;
accessible to a host system via entering requests in a […] submission queue[…] (¶ 36). The host accesses memory by submitting requests to a submission queue;
identify a batch of first requests pending in the submission queue[…] (¶ 36). The storage device utilizes metadata associated with commands pending in a submission queue in order to identify a sequential group of commands (batch of first requests) that are pending in a submission queue.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify memory spaces of Lee to utilize metadata to detect sequential commands while still pending in a submission queue(s), as in Muthiah, because Muthiah suggests that detecting sequential commands pending in submission queues would enable prefetching to be adjusted in order to save time and resources (¶ 36).
Muthiah does not explicitly disclose a plurality of submission queues. While it would arguably have been obvious to modify Muthiah to include multiple submission queues as a mere duplication of parts (MPEP § 2144.04(VI)(B), in the interest of furthering compact prosecution, Examiner has provided Linkovsky, which explicitly discloses this.
Linkovsky discloses the following:
a storage space accessible to a host system via entering requests in a plurality of submission queues (Fig. 3; ¶ 51). The host enters commands into a plurality of submission queues;
a controller configured to: identify a batch of first requests [of] the submission queues (Fig. 1a, controller 102; Abstract). The memory device, which is managed by a controller (Fig. 1, controller 102), identifies read or write streams (a batch of first requests) of multiple submission queues;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the submission queue of Muthiah (combined with Lee) to utilize a plurality of submission queues, as in Linkovsky, because it would be mere duplication of parts (MPEP § 2144.04(VI)(B)).
While Lee discloses a second memory configured to provide a memory space, Lee, Muthiah, and Linkovsky do not explicitly mention memory cells. While it is well known in the art that a DRAM such as that of Lee would contain memory cells, as this is a fundamental storage unit of memory, in the interest of furthering compact prosecution, Examiner has provided Gillis, which explicitly discloses this.
Gillis discloses that DRAM stores data in cells (¶ 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) that the DRAM of Lee (combined with Muthiah and Linkovsky) would contain memory cells, as in Gillis, because Gillis suggests that this is a typical structure for DRAM (¶ 3).
Allowable Subject Matter
Claims 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. It is noted that Examiner attempted to contact Applicant’s attorney, Lehua Wang, to discuss potential Examiner’s amendments to incorporate the subject matter of claim 11 into the independent claims, but Applicant’s attorney declined. Applicant is encouraged to contact Examiner, should Applicant wish to discuss these potential amendments.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-20 filed on 06/23/2026 have been fully considered.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING 35 USC § 112 REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claims 10-16, Applicant argues that claim 10 is not indefinite, as evidenced by Fig. 9. In response, Applicant’s argument has been fully considered, and is deemed persuasive. Accordingly, Examiner’s prior rejection under 35 USC § 112 has been withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claims 1, 10, and 17, Applicant argues Linkovsky and Muthiah do not disclose a separate “memory space” and “storage space”. In response, Applicant’s argument has been fully considered.
Re claims 1 and 17, Applicant’s argument is not deemed persuasive. The language “storage space” and “memory space”, as currently presented, is very broad. They could either refer to the physical spaces on the memory/storage, or to a logical representation thereof (i.e. an address space). They could both be physical spaces, both be logical spaces, or one could be physical and one could be logical. It is noted that there is no claimed requirement that the storage and memory spaces be separately accessible to a host; accordingly, one could be a logical representation of the other, and the host could interact directly with the logical address space and indirectly with the underlying physical space, as in Linkovsky. Moreover, while it is common to refer to volatile memory (i.e. main memory) as “memory” and non-volatile memory (i.e. persistent storage) as “storage”, broadly speaking, these terms are interchangeable; memory stores data, and storage is a type of memory (for example, Flash is often referred to as “memory” even though it is non-volatile and persistent). Accordingly, Examiner does not read “storage space” and “memory space” as necessarily referring to, respectively, a non-volatile storage and a volatile memory. While Applicant has provided one possible interpretation of these limitations, the limitations are not limited to this specific interpretation. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Re claim 10, Applicant’s argument has been fully considered, and is deemed persuasive. Unlike claims 1 and 17, claim 10 explicitly claims that the storage space and memory space comprise respective first and second memory cells. Accordingly, Examiner agrees that the prior rejection was based on an improper interpretation of the claim language. Accordingly, Examiner’s prior rejection under 35 USC § 103 has been withdrawn, and Examiner has provided a new rejection under Lee, Muthiah, Linkovsky, and Gillis. Lee discloses separate address spaces corresponding to a DRAM (memory space) and flash memory (storage space) (¶ 106). Muthiah discloses detecting batches of requests in a submission queue (¶ 36). Linkovsky discloses a plurality of submission queues (Fig. 3; ¶ 51). Gillis discloses that DRAM contains memory cells (¶ 3).
Re claims 2-9 and 18-20, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1 and 17 above, respectively. As this is the soler argument made for allowability, Applicant is directed to Examiner’s comments regarding claims 1 and 17 above, respectively.
Re claims 11-16, Applicant argues that the claims are allowable by virtue of their dependence upon claim 10 above. Accordingly, Applicant is directed to Examiner’s comments regarding claims 11-16, wherein Examiner suggests that the claims have been objected to as dependent upon claim 10, but would be allowable if written in independent form.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 06/23/2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Canepa et al (US 2013/0086336 A1) aggregates large chunks of data from instructions in submission queues (¶ 38).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/ Primary Examiner, Art Unit 2132
