Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16- 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ware et al (US20170286017) hereinafter Ware.
As to claim 16, Ware discloses a computing system comprising: a memory comprising a plurality of dynamic random-access memory (DRAM) banks capable of concurrent access (Fig. 29, and memory 803, and para. 0106); and one or more deterministic processor devices configured to execute instructions in a program order determined in advance by a compiler, wherein the one or more deterministic processor devices are coupled to the near-compute memory (Fig. 29, and controller 801, para. 0106).
As to claim 17, Ware discloses the computing system, wherein the plurality of DRAM banks share a global address space (Fig. 29, and para. 0107, where all memory controls is within this memory space).
As to claim 18, Ware discloses the computing system, wherein the one or more deterministic processor devices comprise a plurality of deterministic processor devices, and wherein each respective processor device of the plurality of processor devices is configured to access each DRAM bank of the plurality of DRAM banks (Fig. 29, and para. 0106).
As to claim 19, Ware discloses the computing system, wherein the one or more deterministic processor devices comprise one or more of: one or more field programmable gate arrays (FPGAs); and one or more application-specific integrated circuits (ASICs) configured for machine-learned inference operations (Fig. 27, and paras. 0104 – 0107 describes the machine learning function, and the silicon embodiment is captured in para. 0112).
As to claim 20, Ware discloses the computing system, further comprising: one or more row buffers configured to store full-row retrieved data obtained via full-row data retrieval from the memory (Fig. 2, and para. 0035); an done or more switching devices configured to route retrieved data from the one or more row buffers to one or more functional units of the one or more deterministic processors, wherein routing the retrieved data comprises reshaping the retrieved data (Fig. 2, where command determines the routing path, para. 0036).
Allowable Subject Matter
Claims 1 – 15 are allowed.
The following is an examiner’s statement of reasons for allowance: Independent claims 1, 14, and their dependents thereof are allowed because the approved terminal disclaimer overcomes the double patent rejection with regards to US12260118.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER ANTHONY DALEY whose telephone number is (571)272-3625. The examiner can normally be reached 7 - 3:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached at 571 2724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
