DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/12/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 11-12, 15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jain et al. (US 7,496,589).
With respect to claim 1, Jain et al. teaches memory (see column 4, lines 9-11; a table is obtained. As discussed above, the table can be in physical volumes such as computer disk drives, ROM disks, or computer tapes) storing compressed sub-tables of a table of data (see column 4, lines 15-17 and 37-39; table is then partitioned into blocks 104 where the number of rows in each block is equal to or less than the block size (i.e., table is partition into sub-tables)… a table that has been partitioned and compressed);
an input circuit configured to receive an input address for the table of data (se column 4, lines 21-27 and lines 37-41; block index that associates row identifiers to block identifiers is created 105. A block identifier is a value or set of values that can be used to access a block. A block number or a block pointer can be used as a block identifier. A block pointer indicates the location of a block in memory. The block identifier and row identifiers are inserted in the block index 113… After the start 201, an index key is obtained 202 and a row identifier is obtained by using the key 203 (i.e., a location/address is received with the key)); and
circuitry configured to: retrieve values from the compressed sub-tables based on the input address (see column 4, lines 48-52; block identifier is used for obtaining the compressed block); and
generate output data based on the retrieved values (see column 4, lines 59-62; Once the compressed block is obtained 205, it is decompressed 206 into a block that contains rows. The row identifier can be used to obtain the desired row from the block 207).
With respect to claim 2, Jain et al. teaches wherein the sub-tables are derived from the table of data (see column 4, lines 15-25 and 37-39; table is then partitioned into blocks 104 where the number of rows in each block is equal to or less than the block size (i.e., table is partition into sub-tables)… a table that has been partitioned and compressed).
With respect to claim 5, Jain et al. teaches wherein the sub-tables include at least one of: Tlb that includes lower bits of the output data, Tust that includes unique sub-tables of the table of data, Tidx that includes indices, Trsh that includes right shift values, or Tbias that includes a minimum value to be added as part of the output data (see column 4, lines 17-20 and 47-44; partitioned tables include index).
With respect to claim 11, Jain et al. teaches receiving, by processing circuitry, a table of data (see column 4, lines 7-9; a table is obtained);
wherein the compressed sub-tables are stored in a memory storing compressed sub-tables of a table of data (see column 4, lines 9-17 and 37-39; a table is obtained. As discussed above, the table can be in physical volumes such as computer disk drives, ROM disks, or computer tapes. Table is then partitioned into blocks 104 where the number of rows in each block is equal to or less than the block size (i.e., table is partition into sub-tables)… a table that has been partitioned and compressed);
retrieving, by the processing circuitry, values from compressed sub-tables of the table (see column 4, lines 59-62; once the compressed block is obtained 205, it is decompressed 206 into a block that contains rows. The row identifier can be used to obtain the desired row from the block 207) of data based on an input address (see column 4, lines 21-27 and lines 37-41; block index that associates row identifiers to block identifiers is created 105. A block identifier is a value or set of values that can be used to access a block. A block number or a block pointer can be used as a block identifier. A block pointer indicates the location of a block in memory. The block identifier and row identifiers are inserted in the block index 113… After the start 201, an index key is obtained 202 and a row identifier is obtained by using the key 203 (i.e., a location/address is received with the key)); and
generating, by the processing circuitry, output data based on the retrieved values (see column 4, lines 59-62; once the compressed block is obtained 205, it is decompressed 206 into a block that contains rows. The row identifier can be used to obtain the desired row from the block 207).
With respect to claim 12, Jain et al. teaches wherein the sub-tables are derived from the table of data (see column 4, lines 15-25 and 37-39; table is then partitioned into blocks 104 where the number of rows in each block is equal to or less than the block size (i.e., table is partition into sub-tables)… a table that has been partitioned and compressed).
With respect to claim 15, Jain et al. teaches wherein the sub-tables include at least one of: Tlb that includes lower bits of the output data, Tust that includes unique sub-tables of the table of data, Tidx that includes indices, Trsh that includes right shift values, or Tbias that includes a minimum value to be added as part of the output data (see column 4, lines 17-20 and 47-44; partitioned tables include index).
With respect to claim 20, Jain et al. teaches compressed sub-tables of the table of data (see column 4, lines 15-17 and 37-39; table is then partitioned into blocks 104 where the number of rows in each block is equal to or less than the block size (i.e., table is partition into sub-tables)… a table that has been partitioned and compressed), wherein the compressed sub-tables are stored in a memory (see column 4, lines 9-17; a table is obtained. As discussed above, the table can be in physical volumes such as computer disk drives, ROM disks, or computer tapes);
receive an input address (see column 4, lines 21-27 and lines 37-41; block index that associates row identifiers to block identifiers is created 105. A block identifier is a value or set of values that can be used to access a block. A block number or a block pointer can be used as a block identifier. A block pointer indicates the location of a block in memory. The block identifier and row identifiers are inserted in the block index 113… After the start 201, an index key is obtained 202 and a row identifier is obtained by using the key 203 (i.e., a location/address is received with the key));
retrieve values from compressed sub-tables of the table of data based on the input address (see column 4, lines 48-52; block identifier is used for obtaining the compressed block); and
generate output data based on the retrieved values (see column 4, lines 59-62; once the compressed block is obtained 205, it is decompressed 206 into a block that contains rows. The row identifier can be used to obtain the desired row from the block 207).
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 2 and 12 above, and further in view of Jarema et al. (US12,019,611).
With respect to claim 3, Jain et al. does not teach wherein a subset of data from the table of data includes a self-similarities subset of data that includes programming instructions to compare received tables of data from a decomposition subset of data and determine whether one or more secondary tables are generable by a primary table.
However, Jarema et al. teaches a primary method for comparison consists of generating indicia for each of the multiple rows of the first and second database table. Then the generated indicia for each of the multiple rows of the first database table are compared with the generated indicia for each of the multiple rows of the second database table, however the comparing occurs without regard to the ordering of the rows in either the first database table or the second database table. If any generated indicia for each of the multiple rows of the first database table are not present in the generated indicia for each of the multiple rows of the second database table, then a first set of mismatched indicia is identified. The converse happens for the second database table's generated indicia to produce a second set of mismatched indicia. A table of differences is populated from the generated indicia which mismatches. or repairs the second database table by using at least one of the sets of mismatched indicia or the table of differences… Breaking the source and target files/tables into subsets to perform the comparisons in parallel may be desirable (e.g. to improve comparison speed and lessen duration) (see column 13, lines 36-40 and column 15, lines 13-54).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to improve performance of the device (see Jarema, column 17, lines 37-39).
With respect to claim 13, Jain et al. does not teach wherein a subset of data from the table of data includes programming instructions to compare received tables of data from a decomposition subset of data and determine whether one or more secondary tables are generable by a primary table.
However, Jarema et al. teaches a primary method for comparison consists of generating indicia for each of the multiple rows of the first and second database table. Then the generated indicia for each of the multiple rows of the first database table are compared with the generated indicia for each of the multiple rows of the second database table, however the comparing occurs without regard to the ordering of the rows in either the first database table or the second database table. If any generated indicia for each of the multiple rows of the first database table are not present in the generated indicia for each of the multiple rows of the second database table, then a first set of mismatched indicia is identified. The converse happens for the second database table's generated indicia to produce a second set of mismatched indicia. A table of differences is populated from the generated indicia which mismatches. or repairs the second database table by using at least one of the sets of mismatched indicia or the table of differences… Breaking the source and target files/tables into subsets to perform the comparisons in parallel may be desirable (e.g. to improve comparison speed and lessen duration) (see column 13, lines 36-40 and column 15, lines 13-54).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to improve performance of the device (see Jarema, column 17, lines 37-39).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 2-3 and 12-13 above, and further in view of Smith-Lacey (US12,333,768).
With respect to claim 4, Jain et al. does not teach wherein the programming instructions further comprise programming instructions to apply a higher bit compression subset of data, wherein to apply a higher bit compression subset of data comprises: first split the received table into a first table of lower bits and second table of higher bits, then apply the decomposition subset of data to the first table of lower bits.
However, Smith-Lacey teaches an n-bit data value is compressed by dividing the n bits of the data value into a first subset of bits and a second subset of bits, the first subset comprising the n−2 most significant bits of the data value and the second subset comprising the two least significant bits of the data value… compression of the first subset is performed using a first compression module (see column 6, lines 46-55). Once the compressed first subset of bits 106 has been decompressed by the first decompression module 109 resulting in a set of decompressed MSBs 111 and the second compressed subset of bits has been decompressed by the second decompression module resulting in a set of decompressed LSBs 112, the set of decompressed MSBs 111 and the set of decompressed LSBs 112 are combined by the combining logic 114 to determine the final decompressed data value 113 (see column 10, lines 50-58).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to give rise to performance improvements that may include one or more of increased computational performance, reduced latency, increased throughput, and/or reduced power consumption (see Smith-Lacey, column 35, lines 26-33).
With respect to claim 14, Jain et al. does not teach teaches wherein the programming instructions further comprise of programming instructions to apply a higher bit compression subset of data, wherein to apply a higher bit compression subset of data comprises: first split the received table into a first table of lower bits and a second table of higher bits, then apply the decomposition subset of data to the first table of lower bits.
However, Smith-Lacey teaches an n-bit data value is compressed by dividing the n bits of the data value into a first subset of bits and a second subset of bits, the first subset comprising the n−2 most significant bits of the data value and the second subset comprising the two least significant bits of the data value… compression of the first subset is performed using a first compression module (see column 6, lines 46-55). Once the compressed first subset of bits 106 has been decompressed by the first decompression module 109 resulting in a set of decompressed MSBs 111 and the second compressed subset of bits has been decompressed by the second decompression module resulting in a set of decompressed LSBs 112, the set of decompressed MSBs 111 and the set of decompressed LSBs 112 are combined by the combining logic 114 to determine the final decompressed data value 113 (see column 10, lines 50-58).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to give rise to performance improvements that may include one or more of increased computational performance, reduced latency, increased throughput, and/or reduced power consumption (see Smith-Lacey, column 35, lines 26-33).
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 1, 5, 11 and 15 above, and further in view of Arelakis et al. (US 2024/0028510).
With respect to claim 6, Jain et al. does not teach wherein Tbias is derived from the table of data by finding the minimum value from each subset of data.
Arelakis et al. teaches a global-base-value table 720 that has four entries 722, 723, 724 and 725 corresponding to B0, B1, B2 and B3, respectively. To select one among the global base values with a minimal difference to the value at hand, the global-base-value table 720 is configured to store the data value 721; using the plurality of differences to establish the smallest difference (i.e., minimum value) and select the base-value table entry corresponding to said difference (see paragraphs 87 and 88).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to achieve a high compression degree/ratio (see Arelakis, paragraph 14 and 141).
With respect to claim 16, Jain et al. does not teach wherein Tbias is derived from the table of data by finding the minimum value from each subset of data.
Arelakis et al. teaches a global-base-value table 720 that has four entries 722, 723, 724 and 725 corresponding to B0, B1, B2 and B3, respectively. To select one among the global base values with a minimal difference to the value at hand, the global-base-value table 720 is configured to store the data value 721; using the plurality of differences to establish the smallest difference (i.e., minimum value) and select the base-value table entry corresponding to said difference (see paragraphs 87 and 88).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to achieve a high compression degree/ratio (see Arelakis, paragraph 14 and 141).
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 1 and 5 above, and further in view of Matula et al. (US 7,962,537).
With respect to claim 7, Jain et al. does not teach wherein the circuitry is further configured to: concatenate an output of the sub-table Tidx with upper bits of the input address to select a unique sub-table from the sub-table Tust.
However, Matula et al teaches select a plurality of bit fields from the subset; extract a plurality of bits from the plurality of bit fields (i.e., high order bits); and determine the table output from the extracted bits by: concatenating the extracted bits and the address to form the table output (see column 7, lines 17-26; and claims 12 and 18).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to improve performance of the system (see Matula, column 1, lines 54-60).
With respect to claim 17, Jain et al. does not teach concatenating, by the processing circuitry, an output of the sub-table Tidx with upper bits of the input address to select a unique sub-table from the sub-table Tust.
However, Matula et al teaches select a plurality of bit fields from the subset; extract a plurality of bits from the plurality of bit fields (i.e., high order bits); and determine the table output from the extracted bits by: concatenating the extracted bits and the address to form the table output (see column 7, lines 17-26; and claims 12 and 18).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to improve performance of the system (see Matula, column 1, lines 54-60).
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 1, 5 and 7 above, and further in view of Mittal (US 2013/0031065).
With respect to claim 8, Jain et al. does not teach wherein the circuitry is further configured to: perform a right shift on a selected number of bits of the sub-table Trsh based in part on the upper bits of the input address.
However, Mittal teaches wherein the second group has at least one 1 in the MSB's, the second group is shifted by conditional shifter 34… conditional shifter 34 shifts the remaining bits A8, A7, A6, A1, A0 to the right by 3 positions, so that A8, A7 are now in the A1, A0 positions (see paragraphs 130 and 133-134).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to improve performance of table structures (see Mittal, paragraph 47).
With respect to claim 18, Jain et al. does not teach performing, by the processing circuitry, a right shift on selected bits of a sub-table Trsh based in part on upper bits of the input address.
However, Mittal teaches wherein the second group has at least one 1 in the MSB's, the second group is shifted by conditional shifter 34… conditional shifter 34 shifts the remaining bits A8, A7, A6, A1, A0 to the right by 3 positions, so that A8, A7 are now in the A1, A0 positions (see paragraphs 130 and 133-134).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to improve performance of table structures (see Mittal, paragraph 47).
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claims 1, 5 and 7 above, and further in view of Mittal (US 2013/0031065).
With respect to claim 9, Jain et al. does not teach wherein the circuitry further comprises: an adder configured to add an output value of a table Tbias and an output value of a right shift or Tust output.
However, Chen et al. teaches wherein when the least significant bit (LSB) which has been right-shifted is 1, then the multiplicand is added to the product obtained from the lookup table in order to arrive at the final product (see column 4, lines 15-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned to improve performance of system (see Chen, column 2, lines 38-48).
With respect to claim 19, Jain et al. does not teach teaches adding an output value of the table Tbias and an output value of a right shift or Tust output.
However, Chen et al. teaches wherein when the least significant bit (LSB) which has been right-shifted is 1, then the multiplicand is added to the product obtained from the lookup table in order to arrive at the final product (see column 4, lines 15-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Jain et al. to include the above mentioned to improve performance of system (see Chen, column 2, lines 38-48).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 7,496,589) as applied to claim 1 above, and further in view of Mesarovic et al. (US 6,504, 496).
With respect to claim 10, Jain et al. does not teach wherein to generate the output data, the circuitry is further configured to concatenate lower bits of the input address with retrieved values from the compressed sub-tables.
However, Mesarovic et al. teaches an address into the second decode table is generated. In step 710, a number of additional bits R, to be drawn from the bitstream as read from the table entry (which may be contained in field 756 of entry 752 in FIG. 7.1). In step 712, R bits (for positive R) are extracted from the bitstream. In step 714, the base address read in step 708 is offset by the value of the R bits extracted from the bitstream in step 712. In other words, the base address is incremented by the value of the R additional bits extracted from the bitstream (see column 11, lines 16-26).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the circuit taught by Jain et al. to include the above mentioned so the decoding technique more efficient (see Mesarovic, column 8, lines 28-33 and column 15, lines 48-53).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yan et al. (US2023/0076744) teaches a detection and utilization of similarities among tables in different data systems.
Loh et al. (US9,477,605) teaches method 300 initiates at block 302 with the issuance of a memory access request to the memory controller 112… tag check logic 204 accesses the tag blocks of one or more rows 222 of the first level memory 106 to determine whether the requested data is in the corresponding row 222 based on a comparison of an address value of the memory access request and the address values stored in the tag blocks of the row 222; in the event that the requested data is determined to be present in a row 222 of the first level memory 106 at block 306, at block 308 the offset logic 206 determines the location of the compressed data block storing the requested data from the location identifier of one or more tags in the row 222, as described above. At block 310, the offset logic 206 and the multiplexer 212 use the location determined at block 308 to select and output the sought-after compressed data block; and if the memory access request is a read access, at block 314 the accessed compressed data block can be decompressed by the decompression logic 216 and the resulting decompressed data block can be provided to the requester or initiator of the memory access request (see column 4, lines 55-67; column 5, lines 1-5 and column 8, lines 41-54).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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