Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations "the first writing" in line 18, and “the second writing” in line 19. There is insufficient antecedent basis for this limitation in the claim. Examiner assumes, based on the specification, that the first writing references the writing of the instruction or set of data of the program in the internal memory, and the second writing references the writing of the parity value in the internal memory, the language used should be consistent and appropriate correction is required. Claim 2 similarly references “the first writing” in lines 6-7 and 9-10. Claim 3 similarly references “the first writing” in lines 14 and 18, and “the second writing” in line 10. Claim 4 similarly references “the second writing” in line 2. Claim 5 similarly references “the first writing” in lines 19-20.
Claim 2 recites the limitation “the transferring” in line 2. There is insufficient antecedent basis for this limitation in the claim. While it seems like this is referencing the “transfer” step in claim 1, it would be clearer if the language was consistent, and appropriate correction is required.
Claim 3 recites the limitation “the first writing unit” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. In this action the first writing unit is interpreted as the unit that writes the instruction or data set of the program into the internal memory, however, appropriate correction is required.
Additionally, these terms are further unclear beyond just lacking antecedent basis. For example, it is unclear whether “the first writing” and “the second writing” (throughout the claims) is referencing a unit that performs those operations, the operations themselves, or the place in internal memory where the data set/parity value is written to. Additionally, claim 1 recites “the first writing of the computer program and the second writing of the instruction or the set”; it is unclear in the context of the claims which imply the instruction or the set are part of the computer program, and there is no first writing of a computer program different from a second writing of the instruction or set contained therein. This is further inconsistent with claim 4 which states “the second writing calculates a parity value of the instruction or the set of data of the computer program… and writes in the internal memory the instruction or set of data of the computer program, which is again read, and the calculated parity value.” Clarification and correction to explicitly describe what the “first writing” and “second writing” is referring to is required. Additionally, claim 2 recites: “transferring when the error has not occurred, to the first writing, the instruction or set of data of the computer program that is read from the internal memory.” If the first writing is meant to be the operation/unit that writes data to the internal memory, it is unclear why data with no errors would be read out from internal memory to the first writing just to be written back to the same place. Examiner believes that this is perhaps intended to reference the teachings of para. 26 of the specification: “When a parity error occurs in an instruction (set of data), the transferring unit 14 transfers, to the CPU 6, an instruction (set of data) that is again read from the external ROM via the second bus 8. On the other hand, when no parity error has occurred in the instruction (set of data), the transferring unit 14 transfers, to the CPU 6, the instruction (set of data) that was read from the RAM 12.” Appropriate correction and or clarification is required.
Claim 2 additionally recites: “wherein the transferring includes… transferring, when the error has not occurred…” While “the transferring” lacks antecedent basis, it seems most likely that it is intended to reference the step of claim 1: “transfer, when the error has occurred…” However, it is unclear and inconsistent to say that the transferring (said to be performed when an error has occurred in claim 1) further includes transferring when an error has not occurred. Clarification and/or correction of what the transferring is exactly referencing and further description of how the occurrence (or lack thereof) of an error effects the transferring is required.
Further, it is unclear whether “the transferring” is referencing an unit that performs the transferring (as would be suggested by claim 3), or if it is referencing the operation of transferring (as would be suggested by claim 2). General correction and/or clarification is required to explicitly explain what exactly each of the limitations of claims 1-5 are referencing and to ensure that the meaning is consistent across the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Muranushi (US Pub. No. 2006/0095829) in view of Yang, (TW1877670B).
Regarding claim 1, Muranushi teaches:
An information processing device having a processor configured to write a computer program, which is read from an external memory, in an internal memory (see para. 68: the loader 4 reads data, such as programs… out of the data area DOA of the external memory 2, following instructions of the processor 3 (step S1). Next, the read-out data and a correspondent check code are written in the data area DIA of the internal memory 5.)
and execute the computer program which is read from the internal memory, (see para. 71: The processor 3 starts the normal operation processing based on the program held in the internal memory 5.)
the information processing device comprising the processor configured to: calculate a parity value of an instruction or a set of data of the computer program read from the external memory, and write the instruction or the set of data and the parity value in the internal memory; (see para. 68: the loader 4 reads data, such as programs… out of the data area DOA of the external memory 2, following instructions of the processor 3 (step S1). Next, the read-out data and a correspondent check code are written in the data area DIA of the internal memory 5 and the check bit memory 6, respectively. And see para. 69: The check code to be written into check bit memory 6 may be generated typically by the data check unit 7, using a data read out from the external memory 2. And see para. 53: The check code may be either even parity or odd parity. And see fig. 8, check bit memory is internal, and is therefore further considered to be internal memory.)
determine, based on the parity value of the instruction or the set of data of the computer program read from the internal memory, presence or absence of an error in the instruction or the set of data of the computer program; (see para. 62: The data check unit 7 herein reads a data of one block in a predetermined block-wise manner out from the internal memory 5, and at the same time reads a check code corresponded thereto out from the check bit memory 6, to thereby detect error in the data (operation OP1A).)
and transfer, when the error has occurred, the instruction or the set of data of the computer program, which is read again from the external memory, to the first writing of the computer program and the second writing of the instruction or the set. (see para. 63: If any error was found in the data, the site of occurrence of the error is posted by the data check unit 7 to the access control unit 8, and an address information correspondent to the data in the external memory 2 is supplied to the loader 4. The loader 4 reads only the data (the block containing the data) having the error detected therein out from the external memory 2 based on thus-supplied address information, and writes (reloads) it to the internal memory 5, to thereby update the erroneous data (operation OP2A).)
Due to the 112B issues with the claim, the concept of “transfer… to the first writing of the computer program and the second writing of the instruction or the set”, is not clear. However, in light of the specification, Examiner has interpreted this last section to mean: when an error has occurred, rewrite the instruction/set from external memory to the internal memory (first writing) and recalculate and rewrite associated parity data. Muranushi does not explicitly teach:
When the error has occurred, recalculate and rewrite parity data associated with the rewritten data.
In the analogous art of error recovery in memory systems, Yang teaches:
When the error has occurred, recalculate and rewrite parity data associated with the rewritten data. (pg. 16, para. 6- pg. 17, para. 1: In step 240, the memory controller 110 reads back the encoded data that was just written from the page cache 121, and decodes the read encoded data through the decoder 140 to determine whether an error has occurred (e.g., performing LDPC decoding to perform error detection). If so, the process proceeds to step 260, where… steps 210-240 are repeated. And see pg. 16, para. 3: first, in step 210, the write data DAT to be written by the host device 50 is read from the cache 113, and the write data DAT is encoded by the encoder 130 to generate encoded data consisting of the write data DAT and the verification data PTY.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Muranushi and Yang before the effective filing date of the claimed invention, to incorporate recalculating parity data with reloading data in response to detection of an error (taught by Yang) into the memory system disclosed by Muranushi, to allow for benefits such as: ensuring that no errors occur due to the influence of alpha particles during the encoding process, or no transmission errors occur during the data transmission to the flash memory (Yang, pg. 3, para. 1). Muranushi doesn’t teach verifying or recalculating check data, which would clearly lead to some disadvantageous situations where the data from the external memory is continually reloaded due to an error in the check data. Yang cures this deficiency by ensuring that when an error occurs, both the data and the check data are recalculated (as either could be the cause of the error).
Regarding claim 2, the combination of Muranushi and Yang teaches the information processing device of claim 1. Muranushi further teaches:
wherein the transferring includes: reloading, when the error has occurred, the instruction or the set of data of the computer program from the external memory, and transferring, when the error has occurred, to the first writing, the instruction or the set of data of the computer program that is again read by the reloading, (see para. 63: If any error was found in the data, the site of occurrence of the error is posted by the data check unit 7 to the access control unit 8, and an address information correspondent to the data in the external memory 2 is supplied to the loader 4. The loader 4 reads only the data (the block containing the data) having the error detected therein out from the external memory 2 based on thus-supplied address information, and writes (reloads) it to the internal memory 5, to thereby update the erroneous data (operation OP2A).)
and transferring, when the error has not occurred, to the first writing, the instruction or the set of data of the computer program that is read from the internal memory. (see para. 75: If the data was judged by the data check unit 7 as having no error (“Y” in step S7), the process returns to step S3 for the normal operation. And see para. 71: The processor 3 starts the normal operation processing based on the program held in the internal memory 5 by the boot operation. And para 71: The processor 3 starts the normal operation processing based on the program held in the internal memory 5 by the boot operation (step S3).) As discussed in the 112B rejection of this claim, this limitation is unclear- particularly what the “first writing” means in this context. Until further clarification is provided this is generally understood in accordance with para. 26 of the instant specification. As you can see, Muranushi teaches that when there are no errors detected, the processor 3 is transferred the program stored in internal memory for normal processing.
Regarding claim 3, the combination of Muranushi and Yang teaches the information processing device of claim 2. Muranushi further teaches:
a first bus that connects the transferring and the first writing unit to each other; and a second bus that connects the external memory and the transferring to each other, (see fig. 1, all arrows are considered to be busses. Loader is considered to be the transferring; internal memory, CPU, or access control unit could be considered to be the first writing unit, as there is no further or previous mention in the claims of what the “first writing unit” is or performs.)
wherein when the error has occurred, the reloading again reads, from the external memory via the second bus, the instruction or the set of data of the computer program and transfers, to the transferring and the second writing, the instruction or the set of data of the computer program that is read again, when the error has occurred, the transferring transfers, to the first writing via the first bus, the instruction or the set of data of the computer program that is again read by the reloading, and when the error has not occurred, the transferring transfers, to the first writing via the first bus, the instruction or the set of data of the computer program that is read from the internal memory. (see para. 63: If any error was found in the data, the site of occurrence of the error is posted by the data check unit 7 to the access control unit 8, and an address information correspondent to the data in the external memory 2 is supplied to the loader 4. The loader 4 reads only the data (the block containing the data) having the error detected therein out from the external memory 2 based on thus-supplied address information, and writes (reloads) it to the internal memory 5, to thereby update the erroneous data (operation OP2A). And see para. 75: If the data was judged by the data check unit 7 as having no error (“Y” in step S7), the process returns to step S3 for the normal operation. And see para. 71: The processor 3 starts the normal operation processing based on the program held in the internal memory 5 by the boot operation. And para 71: The processor 3 starts the normal operation processing based on the program held in the internal memory 5 by the boot operation (step S3).))
Again, there are a plurality of 112B issues here, it is unclear what “the transferring”, “the second writing”, or “the reloading” are referring to. However, Examiner has done their best to interpret the claims in light of the instant specification, and is interpreting this limitation to mean “when an error occurs, data is reloaded from the external memory via a bus and then written into the internal memory (first writing) along with regenerated parity data (second writing). When the error does not occur, data is loaded from internal memory, and used normally.” While Muranushi teaches the majority of the limitations, Muranushi does not explicitly teach:
When the error has occurred, recalculate and rewrite parity data associated with the rewritten data.
Yang teaches:
When the error has occurred, recalculate and rewrite parity data associated with the rewritten data. (pg. 16, para. 6- pg. 17, para. 1: In step 240, the memory controller 110 reads back the encoded data that was just written from the page cache 121, and decodes the read encoded data through the decoder 140 to determine whether an error has occurred (e.g., performing LDPC decoding to perform error detection). If so, the process proceeds to step 260, where… steps 210-240 are repeated. And see pg. 16, para. 3: first, in step 210, the write data DAT to be written by the host device 50 is read from the cache 113, and the write data DAT is encoded by the encoder 130 to generate encoded data consisting of the write data DAT and the verification data PTY.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Muranushi and Yang before the effective filing date of the claimed invention, to incorporate recalculating parity data with reloading data in response to detection of an error (taught by Yang) into the memory system disclosed by Muranushi, to allow for benefits such as: ensuring that no errors occur due to the influence of alpha particles during the encoding process, or no transmission errors occur during the data transmission to the flash memory (Yang, pg. 3, para. 1). Muranushi doesn’t teach verifying or recalculating check data, which would clearly lead to some disadvantageous situations where the data from the external memory is continually reloaded due to an error in the check data. Yang cures this deficiency by ensuring that when an error occurs, both the data and the check data are recalculated (as either could be the cause of the error).
Regarding claim 4, the combination of Muranushi and Yang teaches the information processing device of claim 2. Yang further teaches:
wherein the second writing calculates a parity value of the instruction or the set of data of the computer program that is again read by the reloading, and writes, in the internal memory, the instruction or the set of data of the computer program, which is again read, and the calculated parity value. (pg. 16, para. 6- pg. 17, para. 1: In step 240, the memory controller 110 reads back the encoded data that was just written from the page cache 121, and decodes the read encoded data through the decoder 140 to determine whether an error has occurred (e.g., performing LDPC decoding to perform error detection). If so, the process proceeds to step 260, where… steps 210-240 are repeated. And see pg. 16, para. 3-5: first, in step 210, the write data DAT to be written by the host device 50 is read from the cache 113, and the write data DAT is encoded by the encoder 130 to generate encoded data consisting of the write data DAT and the verification data PTY. Next, in step 220, the encoded data is written to the page cache 121 of the NV memory 120. In step 230, the memory controller 110 sends a write command to the control circuit 123 in the NV memory 120. The control circuit 123 writes the encoded data from the page cache 121 to the NV memory element 122_k.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Muranushi and Yang before the effective filing date of the claimed invention, to incorporate recalculating parity data with reloading data in response to detection of an error (taught by Yang) into the memory system disclosed by Muranushi, to allow for benefits such as: ensuring that no errors occur due to the influence of alpha particles during the encoding process, or no transmission errors occur during the data transmission to the flash memory (Yang, pg. 3, para. 1). Muranushi doesn’t teach verifying or recalculating check data, which would clearly lead to some disadvantageous situations where the data from the external memory is continually reloaded due to an error in the check data. Yang cures this deficiency by ensuring that when an error occurs, both the data and the check data are recalculated (as either could be the cause of the error).
Claim 5 corresponds to claim 1, and is rejected accordingly.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
Prosecution Insights