DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-9, 13-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Osthoff et al (hereinafter Osthoff), US 6126310, in view of Rim et al (hereinafter Rim), US 20210272511 A1.
Referring to claims 1 and 8, taking claim 1 as exemplary, Osthoff discloses a processor comprising:
one or more circuits to perform an instruction to cause one or more other processors to reorder bits of data of network traffic [col. 4, lines 1-15, “transmission link between a data packet transmitter and a data packet receiver”…” a transmitter reordering means for reordering the original information bits of said data packet before transmission using a selected reordering pattern”].
Osthoff does not explicitly disclose reordering based on changes in a state of each bit of data between cycles of a clock.
However, Rim discloses reordering based on changes in a state of each bit of data between cycles of a clock [paragraphs 4, “reducing the number of toggles by reordering the bit sequence may reduce power consumption”; paragraphs 73, 4, fig. 10; fig. 10 shows the bit sequences, each with their own “toggle” count (which is the number of state changes in the sequence); “Additionally or alternatively, the support circuitry 62 may determine using the pixel-by-pixel mode and/or the reorder mode based on the value variance of the predefined number of bits”; “The number of value variances may correspond to a number of toggles”]; hence reordering is based on the value variance/toggles/state changes of the bit sequences; paragraph 45, A row of microdrivers 78 may be activated when a row driver 76 controlling the respective row sends the data clock signal (DATA_CLK) to the microdrivers 78. This may cause the activated microdrivers 78 of the row to receive and store the digital pixel data 70 that is driven by the column drivers 74; the system operates according a DATA_CLK signal, hence reordering would be performed between a first cycle of the system and last cycle of the system].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Rim in the processor of Osthoff to implement, reordering based on changes in a state of each bit of data between cycles of a clock, in order to reduce the number of toggles and reduce power consumption [paragraphs 4, 24].
Referring to claims 2, 9, and 16, taking claim 2 as exemplary, the modified Osthoff discloses the processor of claim 1, wherein reordering the bits of data based on changes in the state of each bit of data between cycles of the clock comprises reordering the bits of data to reduce changes in the state of each bit of data between cycles of the clock [Rim, paragraphs 4, “reducing the number of toggles by reordering the bit sequence may reduce power consumption”].
Referring to claims 3, 10, and 17, taking claim 3 as exemplary, the modified Osthoff discloses the processor of claim 2, wherein reordering the bits of data comprises reordering the bits of data according to a selected reordering option of a plurality of predefined reordering options [Osthoff, col. 4, lines 1-15, “a transmitter reordering means for reordering the original information bits of said data packet before transmission using a selected reordering pattern”].
Referring to claims 6 and 13, taking claim 6 as exemplary, the modified Osthoff discloses the processor of claim 4, wherein the instruction further causes the one or more other processors to identify the selected reordering option for each segment of data within the network traffic [Osthoff, col. 7, lines 22-24, “indicate to the transmitter control means TCM a specific number REORD# of a reordering pattern to be used next for the reordering of information bits”; col. 8, lines 13-16, “In a packet transmission system according to FIG. 1, the packet encoder performs a segmenting and encoding of the information message from the information source IS into a packet”; hence the claimed segment is equivalent to a packet].
Referring to claims 7 and 14, taking claim 7 as exemplary, the modified Osthoff discloses the processor of claim 6, wherein the instruction further causes the one or more other processors to reverse reordering of the bits of data within each segment of data within the network traffic based on the identified, selected reordering option for the segment of data upon receipt of the segment of data [Osthoff, col. 3, lines 60-62, “a receiver reordering means for reordering said received erroneous information bits of said transmitted data packet using said selected reordering pattern”].
Referring to claim 15, Osthoff discloses a communication network switch comprising:
a communication network interface [fig. 1a, see TRANSMITTER TM side]; and
a control circuit [fig. 1a, RM-T] controlling operation of the communication network switch, wherein the control circuit causes the communication network switch to:
receive bits of data of network traffic through the communication network interface [fig. 1a, see Packet Encoder sending bits of network traffic through Transmitter TM];
reorder the received bits of data of network traffic [col. 4, lines 1-15, “a transmitter reordering means for reordering the original information bits of said data packet before transmission using a selected reordering pattern”]; fig. 1a, see RM-T]; and
transmit the reordered bits of data of network traffic through the communication network interface [col. 4, lines 1-15, “transmission link between a data packet transmitter and a data packet receiver”…” a transmitter reordering means for reordering the original information bits of said data packet before transmission using a selected reordering pattern”].
Osthoff does not explicitly disclose a clock; and
based on changes in a state of each bit of data between cycles of the clock.
However, Rim discloses a clock; and
based on changes in a state of each bit of data between cycles of the clock [paragraphs 4, “reducing the number of toggles by reordering the bit sequence may reduce power consumption”; paragraphs 73, 4, fig. 10; fig. 10 shows the bit sequences, each with their own “toggle” count (which is the number of state changes in the sequence); “Additionally or alternatively, the support circuitry 62 may determine using the pixel-by-pixel mode and/or the reorder mode based on the value variance of the predefined number of bits”; “The number of value variances may correspond to a number of toggles”]; hence reordering is based on the value variance/toggles/state changes of the bit sequences; paragraph 45, A row of microdrivers 78 may be activated when a row driver 76 controlling the respective row sends the data clock signal (DATA_CLK) to the microdrivers 78. This may cause the activated microdrivers 78 of the row to receive and store the digital pixel data 70 that is driven by the column drivers 74; the system operates according a DATA_CLK signal, hence reordering would be performed between a first cycle of the system and last cycle of the system].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Rim in the network switch of Osthoff to implement, disclose a clock; and based on changes in a state of each bit of data between cycles of the clock, in order to reduce the number of toggles and reduce power consumption [paragraphs 4, 24].
Referring to claim 20, the modified Osthoff discloses the communication network switch of claim 18, wherein the control circuit further causes the communication network switch to identify the selected reordering option for each segment of data within the network traffic [Osthoff, col. 7, lines 22-24, “indicate to the transmitter control means TCM a specific number REORD# of a reordering pattern to be used next for the reordering of information bits”; col. 8, lines 13-16, “In a packet transmission system according to FIG. 1, the packet encoder performs a segmenting and encoding of the information message from the information source IS into a packet”; hence the claimed segment is equivalent to a packet], and wherein a recipient of each segment of data reverses reordering of the bits of data within the segment of data within the network traffic based on the identified, selected reordering option for the segment of data upon receipt of the segment of data [Osthoff, col. 3, lines 60-62, “a receiver reordering means for reordering said received erroneous information bits of said transmitted data packet using said selected reordering pattern”].
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Osthoff, in view of Rim, as applied to claims 3, 10, and 17 above, and further in view of Byrd, US 20010049805 A1.
Referring to claims 4, 11, and 18, taking claim 4 as exemplary, the modified Osthoff does not explicitly disclose the processor of claim 3, wherein reordering the bits of data comprises reordering bits of data within each segment of data of a plurality of segments of data within the network traffic according to the selected reordering option for the segment of data.
However, Byrd discloses wherein reordering the bits of data comprises reordering bits of data within each segment of data of a plurality of segments of data within the network traffic according to the selected reordering option for the segment of data [claim 20, “a number n of data bits ordered serially in a first format and configured for serially reordering said number n of said data bits of each of said test data packets from said first format into a second format”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Byrd in the processor of the modified Osthoff to implement, wherein reordering the bits of data comprises reordering bits of data within each segment of data of a plurality of segments of data within the network traffic according to the selected reordering option for the segment of data, in order to preserve available memory and allow for more efficient operation [Byrd, paragraph 8].
Allowable Subject Matter
Claims 5, 12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein a number of predefined reordering options in the plurality of predefined reordering options and a size of each segment of data of the plurality of segments of data are determined based on area spend and power consumed by the predefined reordering options in the plurality of predefined reordering options and power consumed to reorder and transmit the bits of data, in combination with other recited limitations in claim 5.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein a number of predefined reordering options in the plurality of predefined reordering options and a size of each segment of data of the plurality of segments of data are determined based on area spend and power consumed by the predefined reordering options in the plurality of predefined reordering options and power consumed to reorder and transmit the bits of data, in combination with other recited limitations in claim 12.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein a number of predefined reordering options in the plurality of predefined reordering options and a size of each segment of data of the plurality of segments of data are determined based on area spend and power consumed by the predefined reordering options in the plurality of predefined reordering options and power consumed to reorder and transmit the bits of data, in combination with other recited limitations in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Golitschek Edler Von Elbwart et al, US 20030110436 A1, discloses wherein the step of reordering comprises interleaving the bits or symbols of the data packets prior to modulation according to a selected one out of a plurality of different interleaving patterns [claim 3].
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/Farley Abad/ Primary Examiner, Art Unit 2181
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