Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Claim(s) 1-20 is/are pending in the application.
- Claim(s) 4-8, 13-16, 18 is/are withdrawn as non-elected
- Claim(s) 1-3, 9-12, 17, 19-20 is/are examined on the merits
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
The application has claimed priority based on prior filed International Patent Application No. PCT/CN2024/073675 filed on January 29, 2023.
Election/Restrictions
Applicant’s election without traverse of Species of figure 6 in the reply filed on November 16, 2025 is acknowledged.
Claims 4-8, 13-14 are withdrawn by Applicant from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 16, 2015.
Further, claims 15-16 are withdrawn by Examiner as being drawn to nonelected species figure 11 and claim 18 is withdrawn by Examiner as being drawn to nonelected species of figure 3.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 21, 2025, June 5, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Element in claim
Element defined in specification or claim
Drive module (claim 1, 3, 9, 10, 17, 19, 20)
Figure 6, element T7 and
claim 11 where “the drive module comprises a seventh transistor”
Light emitting module (claim 1, 9, 17, 19-20
Figure 2, element 13 and paragraphs 0004, 0065-0066, 0095, 0098-0099 where it appears that light emitting module corresponds to organic light emitting diode
data writing module (claim 1, 9, 17, 19-20)
Figure 5, element 12, Figure 6, element T1, T2 and
Claim 1 where “the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor”
Claim 17 where “the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, and the second transistor is an oxide transistor”
Claim 20 where “the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor,”
storage module (claim 9, 19)
Figure 2, element 11, figure 3, element C1, C2 and
Claim 9 where “the storage module comprises a first storage module and a second storage module”
Claim 19 where “the storage module comprises a first storage module and a second storage module”
light- emitting control module (claim 9, 11, 15, 19)
Figure 5, element 14, figure 6, element T11
initialization module (claim 9, 10, 11)
Figure 5, element 161, 162, figure 6, element T9, T10
a first storage module (9-11, 19)
Figure 5, element 111, figure 6, element C1
second storage module(9-11, 19)
Figure 5, element 112, figure 6, element C2
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al, U.S. Patent Publication No. 20180357964.
Consider claim 1, Shin teaches a pixel circuit, comprising: a drive module (see Shin figure 7, element Tdr),
a data writing module (see Shin figure 7, element T1, T2), and
a light-emitting module (see Shin figure 7, element EL),
wherein the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT), and
the data writing module is configured to transmit a data voltage to the drive module (see Shin paragraph 0084, 0096 where in the data writing time Tw, the first and second switch elements T1 and T2 are turned on, and the other switch elements T3, T4 and T5 are turned off. In the data writing time Tw, the source-to-gate voltage Vsg of the driving element Tdr is changed to a data voltage Vdata ); and
the drive module is configured to drive, based on the data voltage, the light-emitting module to emit light (see Shin paragraphs 0096-0097 where emission time Tem, a current Ioled flows in the light emitting element EL depending on the source-to-gate voltage Vsg of the driving element Tdr, and the light emitting element EL can emit light with the current Ioled).
Consider claim 2, Shin teaches all the limitations of claim 1 and further teaches wherein in a display period of the pixel circuit, the second transistor (see Shin figure 7, element T2) is turned on prior to the first transistor (see Shin figure 7, element T1), and the first transistor is turned on in a period in which the second transistor is turned on (see Shin figure 8, element i2, Ts, Tw, EM, SCAN1 and paragraphs 0081-0098 where T2 is turned on (i2-Tw) prior to T1 (Tw) and T1 is turned on while T2 is turned on).
Consider claim 3, Shin teaches all the limitations of claim 1 and further teaches wherein the first transistor and the second transistor are sequentially connected in series between a data line and the drive module (see Shin figure 7, element t1, T2, Tdr, Vdata).
Consider claim 17, Shin teaches a driving method for a pixel circuit, wherein the pixel circuit comprises a drive module (see Shin figure 7, element Tdr),
a data writing module (see Shin figure 7, element T1, T2), and
a light-emitting module (see Shin figure 7, element EL);
the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low- temperature polysilicon transistor, (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), and
the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT); and
the driving method comprises: at a data writing stage, controlling the first transistor and the second transistor to be turned on (see Shin figure 8, element Tw), wherein the second transistor (see Shin figure 7, element T2) is turned on prior to the first transistor (see Shin figure 7, element T1 Note that T2 turns on prior to T1 starting at i2), to transmit a data voltage provided by a data line to the drive module (see Shin paragraph 0084, 0096 where in the data writing time Tw, the first and second switch elements T1 and T2 are turned on, and the other switch elements T3, T4 and T5 are turned off. In the data writing time Tw, the source-to-gate voltage Vsg of the driving element Tdr is changed to a data voltage Vdata );
at a light emitting stage, controlling the first transistor and the second transistor to be turned off (see Shin figure 8, element Tem); and
driving, by the drive module based on the data voltage, the light-emitting module to emit light (see Shin paragraphs 0096-0097 where emission time Tem, a current Ioled flows in the light emitting element EL depending on the source-to-gate voltage Vsg of the driving element Tdr, and the light emitting element EL can emit light with the current Ioled).
Consider claim 20, Shin teaches a display panel, comprising :a pixel circuit (see Shin figure 7), comprising: a drive module (see Shin figure 7, element Tdr),
a data writing module (see Shin figure 7, element T1, T2), and
a light-emitting module (see Shin figure 7, element EL),
wherein the data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT),
the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT), and
the data writing module is configured to transmit a data voltage to the drive module (see Shin paragraph 0084, 0096 where in the data writing time Tw, the first and second switch elements T1 and T2 are turned on, and the other switch elements T3, T4 and T5 are turned off. In the data writing time Tw, the source-to-gate voltage Vsg of the driving element Tdr is changed to a data voltage Vdata ); and
the drive module is configured to drive, based on the data voltage, the light- emitting module to emit light (see Shin paragraphs 0096-0097 where emission time Tem, a current Ioled flows in the light emitting element EL depending on the source-to-gate voltage Vsg of the driving element Tdr, and the light emitting element EL can emit light with the current Ioled).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9-10, 17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gai et al, U.S. Patent Publication No. 20210166623 in view of Shin et al, U.S. Patent Publication No. 20180357964.
Consider claim 1, Gai teaches a pixel circuit, comprising: a drive module (see Gai figure 2, element T3),
a data writing module (see Gai figure 2, element T1), and
a light-emitting module (see Gai figure 2, element L),
wherein the data writing module comprises a first transistor (see Gai figure 2, element T1 and paragraph 0050 where Low temperature poly-silicon thin film transistors (LTPS TFTs) or oxide thin film transistors (Oxide TFTs) are often used)
the data writing module is configured to transmit a data voltage to the drive module (see Gai paragraph 0052-0055 where data writing sub-circuit 10 is configured to input a signal from the second signal terminal S2 to the compensating sub-circuit 20 and the driving sub-circuit 30 under control of a signal from the first signal terminal S1 ); and
the drive module is configured to drive, based on the data voltage, the light-emitting module to emit light (see Gai paragraph 0052-0055 where driving sub-circuit 30 is configured to generate a driving current according to a signal output from the light-emitting control sub-circuit 40 and a signal output from the data writing sub-circuit 10 and input the driving current to the light-emitting sub-circuit 50).
Gai is silent regarding data writing module comprises a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor.
In the same field of endeavor, Shin teaches data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT) so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time (see Sin paragraph 0065).
One of ordinary skill would have been motivated to have modified Gai with the teachings of Shin to incorporate a second transistor that connected in series with T1 of Gai, where the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor as disclosed by Shin so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time using known techniques with predictable results.
Consider claim 9, Gai as modified by Shin teaches all the limitations of claim 1 and further teaches further comprising a storage module (see Gai figure 2, element C1, C2),
a light- emitting control module (see Gai figure 2, element T4),
a compensation module (see Gai figure 2, element T2), and
an initialization module (see Gai figure 2, element T1 and paragraphs 0087-0088 where when the high level turn-on signal is input via the first signal terminal S1 to control the first transistor T1 to be turned on, the reset control signal S2(x) input via the second signal terminal S2 is transmitted to the first end of the first capacitor C1 and the first end of the second capacitor C2, i.e., a node n in FIG. 5, through the first transistor T1, so as to initialize the first capacitor C1 and the second capacitor C2),
wherein the storage module is connected to the drive module, and the storage module is configured to store the data voltage (see Gai figure 2, element C2 and paragraph 0094-0095 where when the high level turn-on signal is input via the first signal terminal S1 to control the first transistor T1 to be turned on, a data signal S2(z) input via the second signal terminal S2 is transmitted to the second capacitor C2 through the first transistor T1 and stored in the second capacitor C2. at the end of the compensation period P2, the voltage at the node n is Vdata, the voltage at the node s is a sum of VSS and Voled0 (VSS+Voled0), and the voltage at the node g is a difference between (a sum of VSS, Voled0, Vth, and Vdata) and Vref (i.e., VSS+Voled0+Vth+Vdata−Vref). Vdata is the voltage of the data signal);
the storage module comprises a first storage module and a second storage module (see Gai figure 2, element C1, C2);
the light-emitting control module, the drive module, and the light-emitting module are sequentially connected between a first power supply and a second power supply (see Gai figure 2, element V1, T5, T3, L, V2));
the first storage module (see Gai figure 2, C1) is connected between the data writing module and a control terminal of the drive module, and the first storage module is configured to couple the data voltage to the drive module (see Gai figure 2, element T1, T3, C2, C1 and paragraph 0094-0095 where when the high level turn-on signal is input via the first signal terminal S1 to control the first transistor T1 to be turned on, a data signal S2(z) input via the second signal terminal S2 is transmitted to the second capacitor C2 through the first transistor T1 and stored in the second capacitor C2, at the end of the compensation period P2, the voltage at the node n is Vdata, the voltage at the node s is a sum of VSS and Voled0 (VSS+Voled0), and the voltage at the node g is a difference between (a sum of VSS, Voled0, Vth, and Vdata) and Vref (i.e., VSS+Voled0+Vth+Vdata−Vref). Vdata is the voltage of the data signal);
non-elected species figure 3), or the compensation module is connected between the control terminal and a first terminal of the drive module, and the first terminal of the drive module is connected to the light-emitting control module (see Gai figure 2, element T2, T3, T4);
the second storage module (see Gai figure 2, element C2) is connected between the data writing module and a second terminal of the drive module or the second storage module is connected between the first storage module and a second terminal of the drive module, and the second storage module is configured to couple a voltage at the second terminal of the drive module to the first storage module (see Gai figure 2, C2, T1, C1, T3 and paragraphs 0094-0095 where when the high level turn-on signal is input via the first signal terminal S1 to control the first transistor T1 to be turned on, a data signal S2(z) input via the second signal terminal S2 is transmitted to the second capacitor C2 through the first transistor T1 and stored in the second capacitor C2, at the end of the compensation period P2, the voltage at the node n is Vdata, the voltage at the node s is a sum of VSS and Voled0 (VSS+Voled0), and the voltage at the node g is a difference between (a sum of VSS, Voled0, Vth, and Vdata) and Vref (i.e., VSS+Voled0+Vth+Vdata−Vref). Vdata is the voltage of the data signal); and
the initialization module is configured to initialize the first storage module and the second storage module (see Gai figure 2, element T1 and paragraphs 0087-0088 where when the high level turn-on signal is input via the first signal terminal S1 to control the first transistor T1 to be turned on, the reset control signal S2(x) input via the second signal terminal S2 is transmitted to the first end of the first capacitor C1 and the first end of the second capacitor C2, i.e., a node n in FIG. 5, through the first transistor T1, so as to initialize the first capacitor C1 and the second capacitor C2).
Consider claim 10, Gai as modified by Shin teaches all the limitations of claim 9 and further teaches wherein the initialization module comprises a first initialization module
Gai is silent regarding a second initialization module; the second initialization module is connected between a second initialization signal line and the second terminal of the drive module. Gai does disclose in paragraph 0060 “that in some other embodiments, the data writing sub-circuit 10 further includes a plurality of switching transistors coupled in parallel with the first transistor T1. The foregoing description is merely an example of the data writing sub-circuit 10. Other structures having a same function as the data writing sub-circuit 10 are not elaborated herein, but all shall be included in the protection scope of the present disclosure”.
Shin teaches an initialization module comprises a first initialization module (see Shin figure 7, element T5, Vref) and a second initialization module (see Shin figure 7, element T4, Vini), the first initialization module is connected between the first initialization signal line and a first terminal of the first storage module (see Shin figure 7, element T5 corresponding to other structures having a same function as Gia initializing structure); and the second initialization module is connected between a second initialization signal line and the second terminal of the drive module (see Shin figure 7, element T4, Vini, Tdr) so as to accurately sense electrical characteristics of a driving element (see Shin paragraph 0069) and initialize the driving element nodes (see Shin paragraph 0074).
One of ordinary skill would have been motivated to have further modified Gai with the teachings of Shin to have an initialization module comprising a first initialization module and a second unitization module so as to so as to accurately sense electrical characteristics of a driving element and initialize the driving element nodes using known techniques with predictable results.
Consider claim 17, Gai teaches a driving method for a pixel circuit, wherein the pixel circuit comprises a drive module (see Gai figure 2, element T3),
a data writing module (see Gai figure 2, element T1), and
a light-emitting module (see Gai figure 2, element L);
the data writing module comprises a first transistor (see Gai figure 2, element T1 and paragraph 0050 where Low temperature poly-silicon thin film transistors (LTPS TFTs) or oxide thin film transistors (Oxide TFTs) are often used)
the driving method comprises: at a data writing stage (see Gai figure 3(a), element P3), controlling the first transistor
at a light emitting stage, controlling the first transistor
driving, by the drive module based on the data voltage, the light-emitting module to emit light (see Gai paragraph 0052-0055 where driving sub-circuit 30 is configured to generate a driving current according to a signal output from the light-emitting control sub-circuit 40 and a signal output from the data writing sub-circuit 10 and input the driving current to the light-emitting sub-circuit 50).
Gai is silent regarding data writing module comprises a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor.
In the same field of endeavor, Shin teaches data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT) so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time (see Sin paragraph 0065).
One of ordinary skill would have been motivated to have modified Gai with the teachings of Shin to incorporate a second transistor that connected in series with T1 of Gai, where the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor as disclosed by Shin so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time using known techniques with predictable results. Incorporation of Shin with Gai would result in having the data writing module comprises a first transistor (see Gai figure 2, element T1 and paragraph 0050 where Low temperature poly-silicon thin film transistors (LTPS TFTs) or oxide thin film transistors (Oxide TFTs) are often used; Shin figure 7, element T1) and a second transistor that are connected in series (see Shin figure 7, element T2), the first transistor is a low- temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), and the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT); and
the driving method comprises: at a data writing stage (see Gai figure 3(a), element P3), controlling the first transistor and the second transistor to be turned on, wherein the second transistor is turned on prior to the first transistor (see Shin figure 8, element Tw, SCAN1, EM where EM turns on T2 prior to SCAN1 turning on T1), to transmit a data voltage provided by a data line to the drive module (see Gai paragraph 0052-0055 where data writing sub-circuit 10 is configured to input a signal from the second signal terminal S2 to the compensating sub-circuit 20 and the driving sub-circuit 30 under control of a signal from the first signal terminal S1);
at a light emitting stage, controlling the first transistor and the second transistor to be turned off (see Gai figure 3(a), element P4; Shin figure 8, element Tem where EM turns off T2 and SCAN1 turns off T1); and
driving, by the drive module based on the data voltage, the light-emitting module to emit light (see Gai paragraph 0052-0055 where driving sub-circuit 30 is configured to generate a driving current according to a signal output from the light-emitting control sub-circuit 40 and a signal output from the data writing sub-circuit 10 and input the driving current to the light-emitting sub-circuit 50).
Consider claim 20, Gai teaches a display panel, comprising: a pixel circuit (see Gai figure 2), comprising: a drive module (see Gai figure 2, element T3),
a data writing module (see Gai figure 2, element T1), and
a light-emitting module (see Gai figure 2, element L),
wherein the data writing module comprises a first transistor (see Gai figure 2, element T1 and paragraph 0050 where Low temperature poly-silicon thin film transistors (LTPS TFTs) or oxide thin film transistors (Oxide TFTs) are often used)
the data writing module is configured to transmit a data voltage to the drive module (see Gai paragraph 0052-0055 where data writing sub-circuit 10 is configured to input a signal from the second signal terminal S2 to the compensating sub-circuit 20 and the driving sub-circuit 30 under control of a signal from the first signal terminal S1 ); and
the drive module is configured to drive, based on the data voltage, the light- emitting module to emit light (see Gai paragraph 0052-0055 where driving sub-circuit 30 is configured to generate a driving current according to a signal output from the light-emitting control sub-circuit 40 and a signal output from the data writing sub-circuit 10 and input the driving current to the light-emitting sub-circuit 50).
Gai is silent regarding data writing module comprises a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor.
In the same field of endeavor, Shin teaches data writing module comprises a first transistor and a second transistor that are connected in series, the first transistor is a low-temperature polysilicon transistor (see Shin figure 7, element T1 and paragraph 0083 where switch elements T1, T3, T4 and T5 and the driving element Tdr may be implemented as a LTPS TFT), the second transistor is an oxide transistor (see Shin figure 7, element T2 and paragraph 0083 where second switch element T2 may be implemented as an oxide TFT) so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time (see Sin paragraph 0065).
One of ordinary skill would have been motivated to have modified Gai with the teachings of Shin to incorporate a second transistor that connected in series with T1 of Gai, where the first transistor is a low-temperature polysilicon transistor, the second transistor is an oxide transistor as disclosed by Shin so as to reduce parasitic capacitance connected to the gate of a driving element for initialization time and sampling time using known techniques with predictable results.
Allowable Subject Matter
Claims 11-12, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed invention recites
Claim 11 “ The pixel circuit according to claim 10, wherein the drive module comprises a seventh transistor, the compensation module comprises an eighth transistor, the first initialization module comprises a ninth transistor, the second initialization module comprises a tenth transistor, and the light-emitting control module comprises an eleventh transistor; the first storage module comprises a first capacitor, and the second storage module comprises a second capacitor; a first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to a first electrode of the second transistor, a second electrode of the second transistor is connected to a first terminal of the first capacitor, a gate of the first transistor is connected to a first scan line, and a gate of the second transistor is connected to a light- emitting control signal line; a first electrode of the ninth transistor is connected to the first initialization signal line, a second electrode of the ninth transistor is connected to the first terminal of the first capacitor, a gate of the ninth transistor is connected to a second scan line, and a second terminal of the first capacitor is electrically connected to a gate of the seventh transistor; a first electrode of the eighth transistor is connected to a first electrode of the seventh transistor, a second electrode of the eighth transistor is connected to the gate of the seventh transistor, and a gate of the eighth transistor is connected to the second scan line; or a first electrode of the eighth transistor is connected to the second electrode of the ninth transistor, a second electrode of the eighth transistor is connected to the second terminal of the first capacitor, and a gate of the eighth transistor is connected to the second scan line; a first terminal of the second capacitor is connected to the first terminal of the first capacitor, and a second terminal of the second capacitor is connected to a second electrode of the seventh transistor, or a first terminal of the second capacitor is connected to the gate of the seventh transistor, and a second terminal of the second capacitor is connected to a second electrode of the seventh transistor; a first electrode of the tenth transistor is connected to the second initialization signal line, a second electrode of the tenth transistor is connected to the second electrode of the seventh transistor, and a gate of the tenth transistor is connected to the light-emitting control signal line; and a first electrode of the eleventh transistor is connected to the first power supply, a second electrode of the eleventh transistor is connected to the first electrode of the seventh transistor, and a gate of the eleventh transistor is connected to the light-emitting control signal line. ”
Claim 9 “ The method according to claim 17, wherein the pixel circuit further comprises a storage module, a light-emitting control module, a compensation module, and an initialization module, and the storage module is connected to the drive module; the storage module comprises a first storage module and a second storage module; the light-emitting control module, the drive module, and the light-emitting module are sequentially connected between a first power supply and a second power supply; the data writing module is connected between the first storage module and the data line; the first storage module is connected between the data writing module and a control terminal of the drive module; the compensation module is connected in parallel to the first storage module, and a first terminal of the drive module is connected to the light- emitting control module, or the compensation module is connected between the control terminal and a first terminal of the drive module, and the first terminal of the drive module is connected to the light-emitting control module; the second storage module is connected between the data writing module and a second terminal of the drive module or the second storage module is connected between the first storage module and a second terminal of the drive module; the initialization module comprises a first initialization module and a second initialization module, the first initialization module is connected between the first initialization signal line and a first terminal of the first storage module, and a second terminal of the first storage module is connected to the control terminal of the drive module; and the second initialization module is connected between a second initialization signal line and the second terminal of the drive module; and the driving method comprises: at an initialization stage, controlling the first transistor, the second transistor, and the second initialization module to be turned off, and controlling the compensation module, the first initialization module, and the light-emitting control module to be turned on, to transmit a first power voltage provided by the first power supply between the first terminal and the control terminal of the drive module, and transmit a first initialization voltage on the first initialization signal line to the first storage module, to initialize the control terminal and the first terminal of the drive module and the first storage module; at a compensation stage, controlling the first transistor and the light-emitting control module to be turned off, and controlling the compensation module, the second transistor, the first initialization module, and the second initialization module to be turned on, to compensate the drive module for a threshold voltage; at a data voltage writing stage, controlling the compensation module, the first initialization module, and the light-emitting control module to be turned off, and controlling the first transistor, the second transistor, and the second initialization module to be turned on, to transmit the data voltage provided by the data line to the drive module; at a light emitting stage, controlling the first transistor, the second transistor, the first initialization module, the second initialization module, and the compensation module to be turned off, and controlling the light-emitting control module to be turned on; and generating, by the drive module, a driving current based on the data voltage to drive the light-emitting module to emit light. ”
The following prior arts are representative of the state of the prior art:
Gai et al, U.S. Patent Publication No. 20210166623 (figures 2-3(a))
Shin et al, U.S. Patent Publication No. 20180357964 (figures 7-8)
Zhang et al, U.S. Patent Publication No. 20220114972 (figure 5)
Wang et al, U.S. Patent Publication No. 20220157223 (figure 4)
The prior arts cited fails to fairly teach or suggest the combined features of the invention including the recited features of dependent claims 11 and 19. Claim 12 is allowable by virtue of being dependent upon a claim reciting allowable subject matter.
These features find support at least at figure 6 of Applicant’s original specification.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 11-12, 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gai et al, U.S. Patent Publication No. 20160171928 (AMOLED pixel unit), Zhang et al, U.S. Patent Publication No. 20220157239 (pixel driving circuit), Wang et al, U.S. Patent Publication No. 20230360600 (pixel driving circuit).
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/Dorothy Harris/Primary Examiner, Art Unit 2625