DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 20 are presented for examination.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119, which papers have been placed of record in the file.
Information Disclosure Statement
The reference listed in the information disclosure statement submitted on 8-11-2025 has been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 2, 9 to 10, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sforzin et al. (USPAP 2024/0103741).
Claim 1:
Sforzin substantially teaches the claimed invention. Sforzin teaches a method and an apparatus for providing multiple error correction code protection levels for a memory system, the method comprising: a host (110) coupled to a memory device (100) providing data (“write data”) to the memory device through a host interface (103) and via of a controller (102) (see par. 0020). Sforzin teaches that the memory device comprises a controller having an error correction (ECC) (104) wherein the error correction circuit includes an encoding component (402) and a decoding component (403) (see par. 0029). Sforzin teaches that the encoding component performs two levels of error protection a first level of protection, maybe the minimum level of error protection and the second level maybe the maximum level of error protection (see par. 0079).
Sforzin teaches that the encoding unit (402) generates a codeword for a first ECC level of protection which is a low ECC protection level (ECC1) and a high ECC protection level which is the second ECC protection level (ECC2) (see par. 0083). Sforzin teaches that the first ECC level comprises a number of parity bits that are different from the second ECC level (see par. 0084). Sforzin further teaches that the first ECC level uses a matrix (P0) that is different from the second matrix (P1) used to generate the second ECC level (see fig. 5A to 5D and par. 0094 et seq.).
Sforzin teaches that the decoding unit performs an ECC operation on the codeword generated by the encoding unit performing an ECC operation according to the first ECC level and the second ECC level (see par. 0090). Sforzin teaches that the decoding unit performs the decoding operation using the first and second ECC levels with a first and second matrix as well as an AND gate wherein an algebraic operation is performed (see par. 0091 et seq.).
Sforzin does not specifically teach the limitation of “sending a first write command sequence to instruct a storage of the write data, the first parity data and the second parity data in the rewritable non-volatile memory module;” however, this teaching is obvious to the teachings of Sforzin because Sforzin teaches that the memory device may have any known memory form such as a NAND memory, etc. (see par. 0031). Sforzin further teaches that an ECC unit having varying error correction capability performs different levels of error correction based on instructions received from the host (see par. 0044 and 0047).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sforzin to include the limitation of: “sending a first write command sequence to instruct a storage of the write data, the first parity data and the second parity data in the rewritable non-volatile memory module;” because Sforzin teaches that a system for providing multiple error correction code protection levels in a memory device comprises a host providing commands to the memory device which may include any of the varying kinds of nonvolatile memories. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for improving power consumption of a memory device by providing multiple error correction code protection level for the memory device as taught by Sforzin (see par. 0015).
As per claim 2, Sforzin teaches that an encoding unit (502) comprises two different matrices (P0 and P1) wherein the first matrix (P0) is added to the payload data to generate the first error correction level generating m bits of parity data. Sforzin teaches that the second matrix (P1) computes parity bits that is a second ECC level higher than the first ECC level using a different matrix (see par. 0097 et seq.). Sforzin teaches that the components of the system may program different states of a memory system wherein more than two states are stored (see par. 0003). Sforzin teaches that the parity data is generated using two different matrices by generating m bits of parity using matrix 551 and matrix 552; which reads on “the first encoding operation and the second encoding operation are performed simultaneously” (see fig. 5D and par. 0103).
Claims 9 and 18:
Sforzin substantially teaches the claimed invention. Sforzin teaches a method and an apparatus for providing multiple error correction code protection levels for a memory system, the method comprising: a host (110) coupled to a memory device (100) providing data (“write data”) to the memory device through a host interface (103) and via of a controller (102) (see par. 0020). Sforzin teaches that the memory device comprises a controller having an error correction (ECC) (104) wherein the error correction circuit includes an encoding component (402) and a decoding component (403) (see par. 0029). Sforzin teaches that the encoding component performs two levels of error protection a first level of protection, maybe the minimum level of error protection and the second level maybe the maximum level of error protection (see par. 0079).
Sforzin teaches that the encoding unit (402) generates a codeword for a first ECC level of protection which is a low ECC protection level (ECC1) and a high ECC protection level which is the second ECC protection level (ECC2) (see par. 0083). Sforzin teaches that the first ECC level comprises a number of parity bits that are different from the second ECC level (see par. 0084). Sforzin further teaches that the first ECC level uses a matrix (P0) that is different from the second matrix (P1) used to generate the second ECC level (see fig. 5A to 5D and par. 0094 et seq.).
Sforzin teaches that the decoding unit performs an ECC operation on the codeword generated by the encoding unit performing an ECC operation according to the first ECC level and the second ECC level (see par. 0090). Sforzin teaches that the decoding unit performs the decoding operation using the first and second ECC levels with a first and second matrix as well as an AND gate wherein an algebraic operation is performed (see par. 0091 et seq.).
Sforzin does not specifically teach the limitation of “a rewritable non-volatile memory module;” however, this teaching is obvious to the teachings of Sforzin because Sforzin teaches that the memory device may have any known memory form such as a NAND memory, or NOR etc. (see par. 0031). Sforzin further teaches that a method for improving power consumption includes having varying error correction capability being performed for different levels of error correction based on instructions received from the host (see par. 0044 and 0047).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Sforzin to include the limitation of: “a rewritable non-volatile memory module;” because Sforzin teaches that a system for improving power consumption in a memory device comprises, providing multiple error correction code protection levels in a memory device that may include any of the varying kinds of nonvolatile memories. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for improving power consumption of a memory device by providing multiple error correction code protection level for the memory device as taught by Sforzin (see par. 0015). As to the further limitation of the claims, Sforzin teaches that the memory controller represents control logic of the device and may be a manager of the memory device (see par. 0022 et seq.).
As per claims 10 and 19, Sforzin teaches that an encoding unit (502) comprises two different matrices (P0 and P1) wherein the first matrix (P0) is added to the payload data to generate the first error correction level generating m bits of parity data. Sforzin teaches that the second matrix (P1) computes parity bits that is a second ECC level higher than the first ECC level using a different matrix (see par. 0097 et seq.). Sforzin teaches that the components of the system may program different states of a memory system wherein more than two states are stored (see par. 0003). Sforzin teaches that the parity data is generated using two different matrices by generating m bits of parity using matrix 551 and matrix 552; which reads on “the first encoding operation and the second encoding operation are performed simultaneously” (see fig. 5D and par. 0103).
Allowable Subject Matter
Claims 3, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 to 8, 12 to 17 and 21 to 26 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record, teaches a method and an apparatus for providing different levels of error correction for a memory device as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: “performing a second encoding operation by the encoding circuit according to the write data, a third sub-matrix in the parity check matrix, and a fourth sub-matrix in the parity check matrix to generate second parity data.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kuo (USPAP 2020/0379844 A1) discloses a method for accessing nonvolatile memories using a memory controller that operates based on a write command.
Teo et al. (USPAP 2013/0019142) Discloses a memory storage device, a memory controller and a method for programming data thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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