DETAILED ACTION
Status of the Claims
The response filed 12/29/25 is entered. Claims 1-4, 6-13, and 15-20 are elected. Claims 5 and 14 are withdrawn. Claims 1-20 are pending.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statements
The information disclosure statement (IDS) submitted on 2/21/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/25.
Claim 2 recites the claim limitations “a first initialization unit”, “a first regulation writing unit”, and “a second initialization unit”, which are not utilized in Species III (Fig. 10).
Claims 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/25.
Claim 10 recites the claim limitation “the data writing module comprises a sixth transistor, wherein a gate of the sixth transistor is connected to a sixth scan signal, a first electrode of the sixth transistor is connected to the data voltage, and a second electrode of the sixth transistor is electrically connected to the first electrode of the drive transistor” which is not in the same configuration in Species III (Fig. 10).
Claims 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species IV, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/25.
Claim 15 recites the claim limitation “the second regulation writing unit comprises: an eleventh transistor, wherein a gate of the eleventh transistor is connected to an eleventh scan signal, a first electrode of the eleventh transistor is electrically connected to the first gate, and a second electrode of the eleventh transistor is connected to a first reference voltage; and a twelfth transistor, wherein a gate of the twelfth transistor is connected to a twelfth scan signal, a first electrode of the twelfth transistor is electrically connected to the first electrode of the drive, and a second electrode of the twelfth transistor is electrically connected to the first electrode of the eleventh transistor; and the preset threshold voltage is 0” which is not in the same configuration in Species III (Fig. 10).
As such, claims 1, 7-9, 11-13, and 18-20 are elected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-9, 11-13, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang, CN-105741779.
In regards to claim 1, Zhang discloses a pixel circuit (Fig. 8, pixel circuit), comprising: a drive module (Fig. 8, T1 transistor) comprising a drive transistor (Fig. 8, T1 transistor), wherein the drive transistor (Fig. 8, T1 transistor) is a dual-gate transistor and comprises a first gate (Fig. 8, gate of T1 at node A) and a second gate (Fig. 8, gate of T1 at node C), and the drive transistor (Fig. 8, T1 transistor) is configured to regulate a threshold voltage of the drive transistor (Fig. 8, T1 transistor) in response to a voltage at the second gate (Fig. 8, gate of T1 at node C), and generate a driving current in response to a voltage at the first gate (Fig. 8, gate of T1 at node A); a threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor) is configured to separately write a preset voltage into the first gate (Fig. 8, gate of T1 at node A) and the second gate (Fig. 8, gate of T1 at node C), and regulate the threshold voltage of the drive transistor (Fig. 8, T1 transistor) to a preset threshold voltage (Par. 0093-0094 “the voltage between the bottom gate sources of the driving transistor T1 is VREF-VER. The switching transistors T2 and T5 are gated to pull the potential of the internal node C high through the high-level line VDD. Since the potential of the internal node B is lower, the voltage difference between the internal nodes C and B is larger, that is, the voltage between the top gate sources of the driving transistor T1 is relatively high, and the top gate source of the driving transistor T1 is between The voltage may adjust the threshold voltage of the driving transistor T1 itself, so the threshold voltage of the driving transistor T1 is relatively low at this time, and may even be a negative value; in one embodiment, the values of the voltages VDD, VREF, and VER are configured to ensure that The threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is smaller than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, so that the driving transistor T1 is in the conducting state. In an embodiment, if VREF=VER, the voltages VDD, VREF, and VER need to be configured so that the threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is negative, thus driving the threshold voltage of the transistor T1. Only when the flying bird is less than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, that is, 0, the driving transistor T1 will be in the conducting state at this time.”); a data writing module (Fig. 8, T3 transistor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the data writing module (Fig. 8, T3 transistor) is configured to write a data voltage (Fig. 8, Vdata) into the drive transistor (Fig. 8, T1 transistor; Fig. 8, T3 applies data voltage Vdata based on scan signal Vscan); a first storage module (Fig. 8, C1 capacitor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the first storage module (Fig. 8, C1 capacitor) is configured to store the voltage at the first gate (Fig. 8, gate of T1 at node A); and a second storage module (Fig. 8, C2 capacitor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the second storage module (Fig. 8, C2 capacitor) is configured to store the voltage at the second gate (Fig. 8, gate of T1 at node C).
In regards to claim 20, Zhang discloses a display panel (Par. 1, display), comprising: pixel circuit (Fig. 8, pixel circuit), comprising: a drive module (Fig. 8, T1 transistor) comprising a drive transistor (Fig. 8, T1 transistor), wherein the drive transistor (Fig. 8, T1 transistor) is a dual-gate transistor and comprises a first gate (Fig. 8, gate of T1 at node A) and a second gate (Fig. 8, gate of T1 at node C), and the drive transistor (Fig. 8, T1 transistor) is configured to regulate a threshold voltage of the drive transistor (Fig. 8, T1 transistor) in response to a voltage at the second gate (Fig. 8, gate of T1 at node C), and generate a driving current in response to a voltage at the first gate (Fig. 8, gate of T1 at node A); a threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor) is configured to separately write a preset voltage into the first gate (Fig. 8, gate of T1 at node A) and the second gate (Fig. 8, gate of T1 at node C), and regulate the threshold voltage of the drive transistor (Fig. 8, T1 transistor) to a preset threshold voltage (Par. 0093-0094 “the voltage between the bottom gate sources of the driving transistor T1 is VREF-VER. The switching transistors T2 and T5 are gated to pull the potential of the internal node C high through the high-level line VDD. Since the potential of the internal node B is lower, the voltage difference between the internal nodes C and B is larger, that is, the voltage between the top gate sources of the driving transistor T1 is relatively high, and the top gate source of the driving transistor T1 is between The voltage may adjust the threshold voltage of the driving transistor T1 itself, so the threshold voltage of the driving transistor T1 is relatively low at this time, and may even be a negative value; in one embodiment, the values of the voltages VDD, VREF, and VER are configured to ensure that The threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is smaller than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, so that the driving transistor T1 is in the conducting state. In an embodiment, if VREF=VER, the voltages VDD, VREF, and VER need to be configured so that the threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is negative, thus driving the threshold voltage of the transistor T1. Only when the flying bird is less than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, that is, 0, the driving transistor T1 will be in the conducting state at this time.”); a data writing module (Fig. 8, T3 transistor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the data writing module (Fig. 8, T3 transistor) is configured to write a data voltage (Fig. 8, Vdata) into the drive transistor (Fig. 8, T1 transistor; Fig. 8, T3 applies data voltage Vdata based on scan signal Vscan); a first storage module (Fig. 8, C1 capacitor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the first storage module (Fig. 8, C1 capacitor) is configured to store the voltage at the first gate (Fig. 8, gate of T1 at node A); and a second storage module (Fig. 8, C2 capacitor) electrically connected to the drive module (Fig. 8, T1 transistor), wherein the second storage module (Fig. 8, C2 capacitor) is configured to store the voltage at the second gate (Fig. 8, gate of T1 at node C).
In regards to claim 7, Zhang discloses the data writing module (Fig. 8, T3 transistor) is electrically connected to the first gate (Fig. 8, gate of T1 at node A) of the drive transistor (Fig. 8, T1 transistor); and the data writing module (Fig. 8, T3 transistor) is configured to write the data voltage (Fig. 8, Vdata) into the first gate (Fig. 8, gate of T1 at node A).
In regards to claim 8, Zhang discloses the data writing module (Fig. 8, T3 transistor) comprises a fifth transistor (Fig. 8, T3 transistor), wherein a gate of the fifth transistor (Fig. 8, T3 transistor) is connected to a fifth scan signal (Fig. 8, Vscan), a first electrode of the fifth transistor (Fig. 8, T3 transistor) is connected to the data voltage (Fig. 8, Vdata), and a second electrode of the fifth transistor (Fig. 8, T3 transistor) is electrically connected to the first gate (Fig. 8, gate of T1 at node A) of the drive transistor (Fig. 8, T1 transistor).
In regards to claim 9, Zhang discloses the first storage module (Fig. 8, C1 capacitor) is connected between the first gate (Fig. 8, gate of T1 at node A) and the first electrode of the drive transistor (Fig. 8, T1 transistor); and the data writing module (Fig. 8, T3 transistor) is electrically connected to the first electrode of the drive transistor (Fig. 8, T1 transistor), and the data writing module (Fig. 8, T3 transistor) is configured to write the data voltage (Fig. 8, Vdata) into the first storage module (Fig. 8, C1 capacitor).
In regards to claim 11, Zhang discloses the threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor) comprises: a second regulation writing unit (Fig. 8, T4 transistor + T6 transistor) electrically connected to the first gate (Fig. 8, gate of T1 at node A) of the drive transistor (Fig. 8, T1 transistor) and electrically connected to a first electrode of the drive transistor (Fig. 8, T1 transistor), wherein the second regulation writing unit (Fig. 8, T4 transistor + T6 transistor) is configured to write the preset threshold voltage into the drive transistor (Fig. 8, T1 transistor; Par. 0093-0094 “the voltage between the bottom gate sources of the driving transistor T1 is VREF-VER. The switching transistors T2 and T5 are gated to pull the potential of the internal node C high through the high-level line VDD. Since the potential of the internal node B is lower, the voltage difference between the internal nodes C and B is larger, that is, the voltage between the top gate sources of the driving transistor T1 is relatively high, and the top gate source of the driving transistor T1 is between The voltage may adjust the threshold voltage of the driving transistor T1 itself, so the threshold voltage of the driving transistor T1 is relatively low at this time, and may even be a negative value; in one embodiment, the values of the voltages VDD, VREF, and VER are configured to ensure that The threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is smaller than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, so that the driving transistor T1 is in the conducting state. In an embodiment, if VREF=VER, the voltages VDD, VREF, and VER need to be configured so that the threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is negative, thus driving the threshold voltage of the transistor T1. Only when the flying bird is less than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, that is, 0, the driving transistor T1 will be in the conducting state at this time.”); and a third regulation writing unit (Fig. 8, T2 transistor + T5 transistor) electrically connected to the second gate (Fig. 8, gate of T1 at node C) of the drive transistor (Fig. 8, T1 transistor), wherein the third regulation writing unit (Fig. 8, T2 transistor + T5 transistor) is configured to write a first fixed voltage (Fig. 8, Vdd) into the second gate (Fig. 8, gate of T1 at node C; Par. 0093-0094 “the voltage between the bottom gate sources of the driving transistor T1 is VREF-VER. The switching transistors T2 and T5 are gated to pull the potential of the internal node C high through the high-level line VDD. Since the potential of the internal node B is lower, the voltage difference between the internal nodes C and B is larger, that is, the voltage between the top gate sources of the driving transistor T1 is relatively high, and the top gate source of the driving transistor T1 is between The voltage may adjust the threshold voltage of the driving transistor T1 itself, so the threshold voltage of the driving transistor T1 is relatively low at this time, and may even be a negative value; in one embodiment, the values of the voltages VDD, VREF, and VER are configured to ensure that The threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is smaller than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, so that the driving transistor T1 is in the conducting state. In an embodiment, if VREF=VER, the voltages VDD, VREF, and VER need to be configured so that the threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is negative, thus driving the threshold voltage of the transistor T1. Only when the flying bird is less than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, that is, 0, the driving transistor T1 will be in the conducting state at this time.”).
In regards to claim 12, Zhang discloses the third regulation writing unit (Fig. 8, T2 transistor + T5 transistor) is further electrically connected to a second electrode of the drive transistor (Fig. 8, T1 transistor), the second electrode of the drive transistor (Fig. 8, T1 transistor) is connected to a first power voltage (Fig. 8, Vdd), and the first power voltage (Fig. 8, Vdd) is reused as the first fixed voltage (Fig. 8, Vdd).
In regards to claim 13, Zhang discloses the third regulation writing unit (Fig. 8, T2 transistor + T5 transistor) comprises a seventh transistor (Fig. 8, T2 transistor), wherein a gate of the seventh transistor (Fig. 8, T2 transistor) is connected to a seventh scan signal (Fig. 8, Vcom), a first electrode of the seventh transistor (Fig. 8, T2 transistor) is electrically connected to the second gate (Fig. 8, gate of T1 at node C), and a second electrode of the seventh transistor (Fig. 8, T2 transistor) is electrically connected to the first fixed voltage (Fig. 8, Vdd), or a second electrode of the seventh transistor (Fig. 8, T2 transistor) is electrically connected to the second electrode of the drive transistor (Fig. 8, T1 transistor); and the third regulation writing unit (Fig. 8, T2 transistor + T5 transistor) further comprises an eighth transistor (Fig. 8, T5 transistor), wherein a gate of the eighth transistor (Fig. 8, T5 transistor) is connected to an eighth scan signal (Fig. 8, Vem), a first electrode of the eighth transistor (Fig. 8, T5 transistor) is electrically connected to the second electrode of the drive transistor (Fig. 8, T1 transistor), and a second electrode of the eighth transistor (Fig. 8, T5 transistor) is connected to the first power voltage (Fig. 8, Vdd).
In regards to claim 18, Zhang discloses the first storage module (Fig. 8, C1 capacitor) comprises a first capacitor (Fig. 8, C1 capacitor), wherein a first electrode of the first capacitor (Fig. 8, C1 capacitor) is electrically connected to the first gate (Fig. 8, gate of T1 at node A), and a second electrode of the first capacitor (Fig. 8, C1 capacitor) is electrically connected to a first electrode of the drive transistor (Fig. 8, T1 transistor); and the second storage module (Fig. 8, C2 capacitor) comprises a second capacitor (Fig. 8, C2 capacitor), wherein a first electrode of the second capacitor (Fig. 8, C2 capacitor) is electrically connected to the second gate (Fig. 8, gate of T1 at node C), and a second electrode of the second capacitor (Fig. 8, C2 capacitor) is electrically connected to the first electrode of the drive transistor (Fig. 8, T1 transistor).
In regards to claim 19, Zhang discloses method for driving a pixel circuit (Fig. 8 pixel circuit), using a pixel circuit (Fig. 8 pixel circuit) according to claim 1, wherein the driving method comprises: at a threshold regulation stage, separately writing, by the threshold voltage regulation module (Fig. 8, T5 transistor + T2 Transistor + T4 transistor + T6 transistor), a preset voltage into the first gate (Fig. 8, gate of T1 at node A) and the second gate (Fig. 8, gate of T1 at node C), and controlling the drive transistor (Fig. 8, T1 transistor) in a self-conducting state to regulate a threshold voltage of the drive transistor (Fig. 8, T1 transistor) to a preset threshold voltage (Par. 0093-0094 “the voltage between the bottom gate sources of the driving transistor T1 is VREF-VER. The switching transistors T2 and T5 are gated to pull the potential of the internal node C high through the high-level line VDD. Since the potential of the internal node B is lower, the voltage difference between the internal nodes C and B is larger, that is, the voltage between the top gate sources of the driving transistor T1 is relatively high, and the top gate source of the driving transistor T1 is between The voltage may adjust the threshold voltage of the driving transistor T1 itself, so the threshold voltage of the driving transistor T1 is relatively low at this time, and may even be a negative value; in one embodiment, the values of the voltages VDD, VREF, and VER are configured to ensure that The threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is smaller than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, so that the driving transistor T1 is in the conducting state. In an embodiment, if VREF=VER, the voltages VDD, VREF, and VER need to be configured so that the threshold voltage of the driving transistor T1 adjusted by the voltage difference between the internal nodes C and B is negative, thus driving the threshold voltage of the transistor T1. Only when the flying bird is less than the voltage VREF-VER between the bottom gate sources of the driving transistor T1 at this time, that is, 0, the driving transistor T1 will be in the conducting state at this time.”); at a data writing stage, writing, by the data writing module (Fig. 8, T3 transistor), a data voltage (Fig. 8, Vdata) into the drive transistor (Fig. 8, T1 transistor; Par. 0095 writing data into the drive transistor); and at a light emitting stage, generating, by the drive module (Fig. 8, T1 transistor), a driving current in response to a voltage at the first gate (Fig. 8, gate of T1 at node A; Par. 0096 generating a drive current to emit light).
Conclusion
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/CORY A ALMEIDA/ Primary Examiner, Art Unit 2628 1/21/26