DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 28-47 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 02/21/2025 are acceptable for examination purposes.
Information Disclosure Statement
The reference(s) listed in the disclosure statement (IDS) submitted on 04/09/202, 08/27/2025, and 2/21/2025 have been considered. The submission complies with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 28-30, 33-40, 43-47 are rejected under 35 U.S.C. 103 as being unpatentable over Hayes et al (U.S. Patent Application No 2017/0116100 A1) et al, hereinafter referred as Hayes, in view of Schmisseur (U.S. Patent Application No 2005/0144382 A1).
As per claim 28, Hayes teaches a system comprising:
a plurality of computing devices (The storage cluster distributes user data across storage nodes housed within a chassis, using erasure coding and redundant copies of metadata; p. 0016-0017) configured to map a plurality of memory blocks to a failure resilient address space (The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier (equates failure resilient address space). This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping; Hayes p. 0028), wherein:
the failure resilient address space spans more than one storage device of a plurality of storage devices (Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment; p. 0016, 0027, 0029), and
Hayes teaches reconstructed data may be written directly from the store queue to the host such as to the host memory in a degraded data read operation (p. 0046). Hayes does not explicitly teach the plurality of computing devices is configured to perform a degraded data read when a particular memory block of the plurality of memory blocks is found to be in error.
However, Schmisseur in an analogous art teaches a degraded data read (reconstructed data may be written directly from the store queue 200 to the host 102 such as to the host memory 106 in a degraded data read operation; Schmisseur p. 0046).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring a degraded data read.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a degraded data read in the system of Hayes because Schmisseur teaches managing data organization to improve fault tolerance or performance, or both (Schmisseur p. 0004).
As per claim 29, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein the plurality of storage devices comprises non-volatile memory (The storage grid includes storage clusters and each of the storage clusters may include non-volatile solid state storage units that are arranged for survivability and decreased vulnerability. The storage clusters are not limited to the use of non-volatile solid state storage as any suitable storage class medium including volatile storage, non-volatile storage, solid state storage, disk drives, or any combinations of storage class medium, may be integrated into the storage clusters. Flash memory is one type of solid-state memory that may be integrated with the embodiments, although the embodiments may be extended to other types of solid-state memory or other storage medium, including non-solid state memory; p. 0015-0016).
As per claim 30, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein the plurality of computing devices is configured to write data into the plurality of memory blocks (When the system has determined that data is to be written, the authority 168 for that data is located as above. When the segment ID for data is already determined the request to write is forwarded to the non-volatile solid state storage 152 currently determined to be the host of the authority 168 determined from the segment. The host CPU 156 of the storage node 150, on which the non-volatile solid state storage 152 and corresponding authority 168 reside, then breaks up or shards the data and transmits the data out to various non-volatile solid state storage 152. The transmitted data is written as a data stripe in accordance with an erasure coding scheme; Hayes p. 0015, 0029).
As per claim 33, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein the plurality of computing devices is configured to update an extent to identify one or more memory blocks of the plurality of memory blocks associated with protecting data being written to the memory block (A segment is a logical container of data in accordance with some embodiments. A segment is an address space between medium address space and physical flash locations, i.e., the data segment number, are in this address space (equates extent). Segments may also contain metadata, which enable data redundancy to be restored (rewritten to different flash locations or devices) without the involvement of higher level software. A series of address-space transformations takes place across an entire storage system. Segment addresses are then translated into physical flash locations. Physical flash locations have an address range bounded by the amount of flash in the system in accordance with some embodiments. Medium addresses and segment addresses are logical containers, and in some embodiments use a 128 bit or larger identifier so as to be practically infinite, with a likelihood of reuse calculated as longer than the expected life of the system; Hayes p. 0031-0032).
As per claim 34, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein the plurality of computing devices is configured to read data from the plurality of memory blocks (In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid state storage and corresponding storage nodes pointed to by the authority. In some embodiments the data is read from flash storage as a data stripe. The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network; p. 0029).
As per claim 35, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein a data read from each memory block of the plurality of memory blocks is checked for errors using a distributed erasure code (The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network; p. 0029).
As per claim 36, Hayes in view of Schmisseur teaches the system of claim 28. Hayes also teaches wherein the system comprises the plurality of storage devices (Each storage node may be one or more storage servers and each storage server is connected to one or more non-volatile solid state memory units, which may be referred to as storage units. storage cluster 160, with multiple storage nodes 150 and internal solid-state memory coupled to each storage node to provide network attached storage or storage area network, in accordance with some embodiments; p. 0018-0019).
As per claim 37, Hayes in view of Schmisseur teaches the system of claim 28,
wherein the degraded data read comprises regenerating the particular memory block from one or more memory blocks other than the particular memory block of the plurality of memory blocks (a storage node in the cluster to fail, with the system remaining operational, since the data can be reconstructed from other storage nodes and thus remain available for input and output operations. The data can be read from, recovered or reconstructed from any two of the storage cluster; p. 0016, 0043-0044).
As per claim 38, Hayes teaches a method for accessing storage media, the method comprising:
distributing a failure resilient address space comprising a plurality of memory blocks, across a plurality of storage devices, via a plurality of computing devices (The storage cluster distributes user data across storage nodes housed within a chassis, using erasure coding and redundant copies of metadata; p. 0016-0017); and
performing a degraded data read when a particular memory block of the plurality of memory blocks is found to be in error (The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier (equates failure resilient address space). This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping; p. 0028)(Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment; p. 0016, 0027, 0029).
Hayes teaches reconstructed data may be written directly from the store queue to the host such as to the host memory in a degraded data read operation (p. 0046). Hayes does not explicitly teach performing a degraded data read when a particular memory block of the plurality of memory block is found to be in error.
However, Schmisseur in an analogous art teaches a degraded data read (reconstructed data may be written directly from the store queue 200 to the host 102 such as to the host memory 106 in a degraded data read operation; p. 0046).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring a degraded data read.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a degraded data read in the system of Hayes because Schmisseur teaches managing data organization to improve fault tolerance or performance, or both (p. 0004).
As per claim 39, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein the plurality of storage devices comprises non-volatile memory (The storage grid includes storage clusters and each of the storage clusters may include non-volatile solid state storage units that are arranged for survivability and decreased vulnerability. The storage clusters are not limited to the use of non-volatile solid state storage as any suitable storage class medium including volatile storage, non-volatile storage, solid state storage, disk drives, or any combinations of storage class medium, may be integrated into the storage clusters. Flash memory is one type of solid-state memory that may be integrated with the embodiments, although the embodiments may be extended to other types of solid-state memory or other storage medium, including non-solid state memory; p. 0015-0016).
As per claim 40, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein the method comprises writing data into the plurality of memory blocks (When the system has determined that data is to be written, the authority 168 for that data is located as above. When the segment ID for data is already determined the request to write is forwarded to the non-volatile solid state storage 152 currently determined to be the host of the authority 168 determined from the segment. The host CPU 156 of the storage node 150, on which the non-volatile solid state storage 152 and corresponding authority 168 reside, then breaks up or shards the data and transmits the data out to various non-volatile solid state storage 152. The transmitted data is written as a data stripe in accordance with an erasure coding scheme; p. 0015, 0029).
As per claim 43, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein the method comprises updating an extent to identify one or more memory blocks of the plurality of memory blocks associated with protecting data being written to the memory block (A segment is a logical container of data in accordance with some embodiments. A segment is an address space between medium address space and physical flash locations, i.e., the data segment number, are in this address space (equates extent). Segments may also contain metadata, which enable data redundancy to be restored (rewritten to different flash locations or devices) without the involvement of higher level software. A series of address-space transformations takes place across an entire storage system. Segment addresses are then translated into physical flash locations. Physical flash locations have an address range bounded by the amount of flash in the system in accordance with some embodiments. Medium addresses and segment addresses are logical containers, and in some embodiments use a 128 bit or larger identifier so as to be practically infinite, with a likelihood of reuse calculated as longer than the expected life of the system; p. 0031-0032).
As per claim 44, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein the method comprises reading data from the plurality of memory blocks (In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid state storage and corresponding storage nodes pointed to by the authority. In some embodiments the data is read from flash storage as a data stripe. The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network; p. 0029).
As per claim 45, Hayes in view of Schmisseur teaches the method of claim 38, Hayes also teaches wherein the method comprises checking data read from each memory block of the plurality of memory blocks for errors using a distributed erasure code (The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network; p. 0029).
As per claim 46, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein the method comprises managing the failure resilient address space via metadata (Data and metadata is stored by a set of underlying storage layouts that are optimized for varying workload patterns and storage devices. These layouts incorporate multiple redundancy schemes, compression formats and index algorithms. Some of these layouts store information about authorities and authority masters, while others store file metadata and file data; p. 0033).
As per claim 47, Hayes in view of Schmisseur teaches the method of claim 38. Hayes also teaches wherein performing the degraded data read comprises regenerating the particular memory block from one or more memory blocks other than the particular memory block of the plurality of memory blocks (a storage node in the cluster to fail, with the system remaining operational, since the data can be reconstructed from other storage nodes and thus remain available for input and output operations. The data can be read from, recovered or reconstructed from any two of the storage cluster; p. 0016, 0043-0044).
Claims 31, 32, 41, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Hayes in view of Schmisseur and YADAPPANAVAR et al (U.S. Patent No 2012/0158647 A1), hereinafter referred as YADAPPANAVAR.
As per claim 31, Hayes in view of Schmisseur teaches the system of claim 28.
Hayes in view of Schmisseur fail to teach wherein data to be written to a memory block of the plurality of memory blocks is compressed to provide space for a journal associated with data written into the plurality of memory blocks.
However, Schmisseur in an analogous art teaches wherein data to be written to a memory block of the plurality of memory blocks is compressed to provide space for a journal associated with data written into the plurality of memory blocks (the compressed data is first stored in a different sub-block and then copied to sub-block 308 to avoid in-place data corruption. In another embodiment, at step 912, to avoid in-place data corruption, the data currently stored in sub-block 308 is stored in a journaling region and then the compressed data is stored in sub-block 308. over-written; p. 0056, 0063).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring the written data to be compressed for a journal associated with data written into memory blocks.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ compressing written data for a journal in the system of Hayes because Schmisseur teaches block compression to avoid in-place data corruption, the data currently stored in sub-block 308 is stored in a journaling region and then the compressed data is stored in sub-block 308. over-written (p. 0056).
As per claim 32, Hayes in view of Schmisseur teaches the system of claim 28.
Hayes in view of Schmisseur fails to teach wherein data to be written to a memory block of the plurality of memory blocks is padded with data previously written into a portion of the memory block.
However, Schmisseur in an analogous art teaches wherein data to be written to a memory block of the plurality of memory blocks is padded with data previously written into a portion of the memory block (VMFS 216 patches the decompressed data with the write data included in the write request and received from the client. At step 908, VMFS 216 re-compresses the patched data according to the block compression type; p. 0055) (compression manager 316 appends padding bits to the end of the compressed substream to fill the corresponding pre-determined portion; p. 0043).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring the written data to be padded with data previously written into a portion of the memory block.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ padding written data into the memory block in the system of Hayes because Schmisseur teaches re-compressing the patched data to fill the corresponding pre-determined portion (p. 0055).
As per claim 41, Hayes in view of Schmisseur teaches the method of claim 38.
Hayes in view of Schmisseur fails to teach wherein the method comprises compressing data to be written to a memory block of the plurality of memory blocks to provide space for a journal associated with data written into the plurality of memory blocks.
However, Schmisseur in an analogous art teaches wherein the method comprises compressing data to be written to a memory block of the plurality of memory blocks to provide space for a journal associated with data written into the plurality of memory blocks (the compressed data is first stored in a different sub-block and then copied to sub-block 308 to avoid in-place data corruption. In another embodiment, at step 912, to avoid in-place data corruption, the data currently stored in sub-block 308 is stored in a journaling region and then the compressed data is stored in sub-block 308. over-written; p. 0056, 0063).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring the written data to be compressed for a journal associated with data written into memory blocks.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ compressing written data for a journal in the system of Hayes because Schmisseur teaches block compression to avoid in-place data corruption, the data currently stored in sub-block 308 is stored in a journaling region and then the compressed data is stored in sub-block 308. over-written (p. 0056).
As per claim 42, Hayes in view of Schmisseur teaches the method of claim 38. Hayes in view of Schmisseur fails to teach wherein the method comprises padding data to be written to a memory block of the plurality of memory blocks with data previously written into a portion of the memory block.
However, Schmisseur in an analogous art teaches wherein the method comprises padding data to be written to a memory block of the plurality of memory blocks with data previously written into a portion of the memory block (VMFS 216 patches the decompressed data with the write data included in the write request and received from the client. At step 908, VMFS 216 re-compresses the patched data according to the block compression type; p. 0055) (compression manager 316 appends padding bits to the end of the compressed substream to fill the corresponding pre-determined portion; p. 0043).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Hayes with the teachings of Schmisseur by configuring the written data to be padded with data previously written into a portion of the memory block.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ padding written data into the memory block in the system of Hayes because Schmisseur teaches re-compressing the patched data to fill the corresponding pre-determined portion (p. 0055).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
Liu et al (U.S. Patent Application No 20260127080 A1) teaches a method of performing data recovery after a die failure in a memory device includes: identifying, among a plurality of dies of the memory device, a first die experiencing a failure; identifying, by iterating over an address space associated with the first die, a valid data item stored on the first die; responsive to determining that a data recovery workload condition is satisfied, recovering the valid data item; and storing the valid data item on a second die of the plurality of dies.
ENGEL et al (U.S. Patent Application No 20250291674 A1) teaches a set of correctable errors in a data segment stored at one or more storage devices is detected. Corresponding corrections for the set of correctable errors is stored in a data structure that is separate from the data segment. A read operation is performed to read data from the data segment by utilizing the corresponding corrections to replace one or more of the set of correctable errors in the data segment with the corresponding correction in the data structure.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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