Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 02/21/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 7, 9, 14, 15, 16, and 19 are objected to because of the following informalities: Regarding claim 1, in line 3, “proportional of” appears that it should read as “proportional to”, because of grammar;
in line 16, “a reference voltage” appears that it should read as “the voltage reference”, because of antecedent basis, a voltage reference having been previously recited in line 7.
Regarding claim 7, in line 3, “the amplifier including a first input” appears that it should read as “the amplifier includes a first input”, because of grammar, the clause otherwise lacking a finite verb.
Regarding claim 9, in line 2, “in a second state the control circuit” appears that it should read as “in a second state, the control circuit”, because of punctuation.
Regarding claim 14, in line 5, “subsequent to first phase” appears that it should read as “subsequent to the first phase”, because of antecedent basis.
Regarding claim 15, in line 2, “control circuit is configurable to charge” appears that it should read as “the control circuit is configurable to charge”, because of antecedent basis.
Regarding claim 16, in line 2-3, “a comparison between a second voltage on a bottom plate of the capacitor with a reference voltage” appears that it should read as “a comparison between a second voltage on a bottom plate of the capacitor and a reference voltage”, because of grammar.
Regarding claim 19, in line 2, “the first phase, the second phase, and the comparison is a test” appears that it should read as “the first phase, the second phase, and the comparison are a test”, because of grammar;
in line 3, “a plurality of the tests” appears that it should read as “a plurality of tests”, because of antecedent basis;
in line 4-5, “the plurality of the tests” appears that it should read as “the plurality of tests”, because of antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 19, the recitation “N number of the plurality of the tests” renders the claim indefinite. The claim does not define N, does not recite a value or a range for N, and does not recite a relationship between N and the number of tests in the recited plurality. It is therefore unclear how many of the tests must have the second voltage less than the reference voltage before the control circuit outputs the fault signal, and the metes and bounds of the claim cannot be determined.
The ambiguity is compounded by the specification, which uses N to denote the total number of short detection tests evaluated rather than the number of tests that have failed (see [0035] of the specification “If M of the last N short detection tests have failed, then a short across the pass transistor 102 is deemed detected in block 406.”), such that N as recited in claim 19 and N as used in the specification denote different quantities.
For purposes of examination, “N number of the plurality of the tests” is construed as one or more of the tests of the recited plurality.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12,261,429. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are broader in scope than, and are encompassed by, the corresponding claims of U.S. Patent No. 12,261,429. The correspondence between the conflicting claims, limitation by limitation, is set forth in the table below.
19/059,395
U.S. Patent No. 12,261,429
Claim 1
(a) An apparatus, comprising:
(b) a first current circuit coupled in series with a first resistor, wherein the first current circuit is configurable to output a first current proportional of a second current of a first transistor;
(c) a capacitor circuit coupled to the first current circuit and the first resistor, the capacitor circuit including a capacitor;
(d) a comparator including a first input coupled to a voltage reference, a second input coupled to the capacitor circuit, and an output;
(e) a control circuit including an input coupled to the output of the comparator, a first output coupled to the capacitor circuit, and a second output; and
(f) a second current circuit including a second transistor, the second current circuit coupled to the first transistor and the second output of the control circuit;
(g) wherein the control circuit is configurable to: enable the second transistor to receive the second current;
(h) enable the capacitor circuit to output a first voltage;
(i) receive a comparison of the first voltage and a reference voltage; and
(j) determine a fault condition based on the comparison.
Claims 8-12 and 15
(a) [claim 8] A short detection circuit, comprising:
(b) [claim 11] a second current source coupled to the second transistor, the second current source configured to generate a current that is representative of the sense current; and a second resistor coupled between the second current source and the ground terminal; [claim 8] a second transistor coupled to the first transistor, the second transistor configured to conduct a sense current
(c) [claim 8] a switched capacitor circuit coupled to the second transistor
(d) [claim 8] a comparator having an output, a first comparator input, and a second comparator input, in which the first comparator input is coupled to the switched capacitor circuit; [claim 15] the second comparator input is coupled to a reference voltage circuit configured to generate the short threshold voltage
(e) [claim 9] the switch configured to switchably connect the current source to the first transistor; [claim 10] the amplifier is configured to provide a control signal at the amplifier output responsive to voltages at the first and second amplifier inputs
(f) [claim 8] a switched load circuit coupled to the first transistor, the switched load circuit configured to switchably draw a test current; [claim 10] a third transistor having a control terminal, and the third transistor is configured to conduct the test current responsive to the control signal
(g) [claim 8] the sense current includes first and second portions, the first portion is representative of the load current, and the second portion is representative of the test current
(h) [claim 8] the switched capacitor circuit configured to generate a short detection voltage representative of the second portion
(i) [claim 8] the comparator is configured to compare the short detection voltage to a short threshold voltage
(j) [claim 8] a comparator having an output
Claim 2
the first current circuit includes a current mirror circuit.
Claim 12
[claim 12] wherein the second current source includes a current mirror circuit configured to generate the current that is representative of the sense current based on the sense current.
Claim 3
(a) the capacitor circuit includes a first switch coupled to the first output of the control circuit,
(b) a second switch coupled to a third output of the control circuit,
(c) and a third switch coupled to a fourth output of the control circuit.
Claims 13 and 14
(a) [claim 14] a second switch coupled between the bottom plate and the ground terminal, the second switch configured to switchably connect the bottom plate to the ground terminal
(b) [claim 13] a first switch coupled between the second resistor and the top plate, the first switch configured to switchably connect the top plate to the second current source
(c) [claim 14] a third switch coupled between the bottom plate and the first comparator input, the third switch configured to switchably connect the bottom plate to the first comparator input
Claim 4
(a) the capacitor includes a top plate and a bottom plate;
(b) the top plate of the capacitor is coupled to the second switch; and
(c) the bottom plate of the capacitor is coupled to the first switch and the third switch.
Claims 13 and 14
(a) [claim 13] a capacitor having a top plate and a bottom plate
(b) [claim 13] a first switch coupled between the second resistor and the top plate
(c) [claim 14] a second switch coupled between the bottom plate and the ground terminal; and a third switch coupled between the bottom plate and the first comparator input
Claim 5
the second current circuit includes a fourth switch coupled to the second output of the control circuit.
Claim 9
[claim 9] a switch coupled between the first transistor and the current source, the switch configured to switchably connect the current source to the first transistor.
Claim 6
(a) the fourth switch is coupled between the first transistor and the second transistor; and
(b) a second resistor is coupled to the second transistor.
Claims 9 and 10
(a) [claim 9] a switch coupled between the first transistor and the current source; [claim 10] the third transistor is coupled between the first resistor terminal and the switch
(b) [claim 10] a resistor having first and second resistor terminals, in which the first resistor terminal is coupled to the third transistor, the second resistor terminal is coupled to a ground terminal
Claim 7
(a) the second current circuit includes an amplifier; and
(b) the amplifier including a first input coupled to the second transistor,
(c) a second input coupled to a bandgap voltage circuit,(d) and an output coupled to a control terminal of the second transistor.
Claims 3 and 10
(a) [claim 10] an amplifier having an amplifier output and first and second amplifier inputs
(b) [claim 10] the first amplifier input is coupled to the first resistor terminal, in which the first resistor terminal is coupled to the third transistor
(c) [claim 3] the second amplifier input is coupled to a bandgap voltage circuit
(d) [claim 10] the amplifier output is coupled to the control terminal, and the third transistor is configured to conduct the test current responsive to the control signal
Claim 8
(a) in a first state, the control circuit is configurable to: open the fourth switch;
(b) close the third switch; and
(c) close the second switch.
Claims 9, 13, and 14
(a) [claim 9] the switch configured to switchably connect the current source to the first transistor
(b) [claim 14] the second switch configured to switchably connect the bottom plate to the ground terminal
(c) [claim 13] the first switch configured to switchably connect the top plate to the second current source
Claim 9
(a) in a second state the control circuit is configurable to: close the fourth switch;
(b) open the third switch;
(c) close the second switch; and
(d) close the first switch.
Claims 9, 13, and 14
(a) [claim 9] the switch configured to switchably connect the current source to the first transistor
(b) [claim 14] the second switch configured to switchably connect the bottom plate to the ground terminal
(c) [claim 13] the first switch configured to switchably connect the top plate to the second current source
(d) [claim 14] a third switch coupled between the bottom plate and the first comparator input, the third switch configured to switchably connect the bottom plate to the first comparator input
Claim 10
the first current is a scaled current of the second current.
Claims 11 and 12
[claim 11] the second current source configured to generate a current that is representative of the sense current; [claim 12] a current mirror circuit configured to generate the current that is representative of the sense current based on the sense current.
Claim 11
(a) A device, comprising:
(b) a first transistor coupled to a second transistor, wherein a second current through the second transistor is proportional to a first current through the first transistor;
(c) a first current circuit coupled to a first resistor, wherein the first current circuit outputs a third current based on the second current;
(d) a second current circuit coupled to the first transistor;
(e) a capacitor circuit coupled to the first current circuit and the first resistor;
(f) a comparator coupled to the capacitor circuit; and
(g) a control circuit coupled to the comparator, the capacitor circuit, and the second current circuit.
Claims 1, 3, and 7
(a) [claim 1] A short detection circuit, comprising:
(b) [claim 1] a first transistor having a first current terminal, second current terminal, and a first control terminal; a second transistor having a third current terminal, a fourth current terminal, and a second control terminal, in which: the third current terminal is coupled to the first current terminal; and the second control terminal is coupled to the first control terminal
(c) [claim 1] a current source having a current output and a current input, in which the current input is coupled to the fourth current terminal; a second resistor coupled between the current output and the ground terminal; [claim 7] the current source includes a current mirror circuit configured to generate a first current conducted by the second resistor based on a second current conducted by the second transistor
(d) [claim 3] a third transistor having a fifth current terminal, a sixth current terminal, and a third control terminal, in which the sixth current terminal is coupled to the first terminal of the first resistor; wherein the switch is coupled between the sixth current terminal and the second current terminal
(e) [claim 1] a switched capacitor circuit coupled between the current output and the ground terminal
(f) [claim 1] a comparator having a comparator output, a first comparator input, and a second comparator input, in which: the first comparator input is coupled to the switched capacitor circuit
(g) [claim 3] an amplifier having an amplifier output, a first amplifier input, and a second amplifier input, in which the amplifier output is coupled to the third control terminal
Claim 12
the third current is equal to the second current.
Claim 7
[claim 7] a current mirror circuit configured to generate a first current conducted by the second resistor based on a second current conducted by the second transistor.
Claim 13
(a) the capacitor circuit includes a first switch, a second switch, and a third switch;
(b) the second current circuit includes a fourth switch; and
(c) the first switch, the second switch, the third switch, and the fourth switch are respectively coupled to the control circuit.
Claims 2, 4, and 5
(a) [claim 4] a switch coupled between the top plate and the current output; [claim 5] a second switch coupled between the bottom plate and the ground terminal; and a third switch coupled between the bottom plate and the first comparator input
(b) [claim 2] a switch coupled between the second current terminal and a first terminal of the first resistor
(c) [claim 5] the switch is a first switch; and the switched capacitor circuit includes: a second switch coupled between the bottom plate and the ground terminal; and a third switch coupled between the bottom plate and the first comparator input
Claim 14
(a) in a first phase, the control circuit is configurable to: open the fourth switch; and close the third switch; and
(b) in a second phase subsequent to first phase, the control circuit is configurable to: close the fourth switch; and open the third switch.
Claims 2 and 5
(a) [claim 2] a switch coupled between the second current terminal and a first terminal of the first resistor; [claim 5] a second switch coupled between the bottom plate and the ground terminal
(b) [claim 2] a switch coupled between the second current terminal and a first terminal of the first resistor; [claim 5] a second switch coupled between the bottom plate and the ground terminal
Claim 15
control circuit is configurable to charge a capacitor in the capacitor circuit during the first phase to a first voltage.
Claims 4 and 5
[claim 4] a capacitor having a top plate and a bottom plate; and a switch coupled between the top plate and the current output; [claim 5] a second switch coupled between the bottom plate and the ground terminal
Claim 16
(a) subsequent to the second phase, the comparator outputs a comparison between a second voltage on a bottom plate of the capacitor
(b) with a reference voltage.
Claims 1 and 5
(a) [claim 5] a third switch coupled between the bottom plate and the first comparator input; [claim 1] the first comparator input is coupled to the switched capacitor circuit
(b) [claim 1] the second comparator input is coupled to a reference voltage terminal
Claim 17
the control circuit is configurable to output a fault signal in response to the comparison.
Claims 1 and 8
[claim 1] a comparator having a comparator output; [claim 8] the comparator is configured to compare the short detection voltage to a short threshold voltage
Claim 18
in response to the second voltage being less than the reference voltage, the control circuit is configurable to output a fault signal.
Claims 1, 8, and 15
[claim 8] the comparator is configured to compare the short detection voltage to a short threshold voltage; [claim 15] the second comparator input is coupled to a reference voltage circuit configured to generate the short threshold voltage; [claim 1] a comparator having a comparator output
Claim 19
(a) the first phase, the second phase, and the comparison is a test;
(b) the control circuit is configurable to perform a plurality of the tests; and
(c) the control circuit is configurable to output a fault signal in response to N number of the plurality of the tests having the second voltage being less than the reference voltage.
Claims 1, 8, and 15
(a) [claim 8] the comparator is configured to compare the short detection voltage to a short threshold voltage
(b) [claim 8] the comparator is configured to compare the short detection voltage to a short threshold voltage; the recited plurality of tests is a duplication of the comparison already recited
(c) [claim 15] the second comparator input is coupled to a reference voltage circuit configured to generate the short threshold voltage; [claim 1] a comparator having a comparator output
Claim 20
(a) A system, comprising:
(b) a power supply;
(c) a load circuit; and
(d) a circuit coupled to the power supply and the load circuit, wherein the circuit includes:
(e) a first transistor configurable to conduct a load current from the power supply to the load circuit;
(f) a switched load circuit coupled to the first transistor;
(g) a second transistor coupled to the first transistor, the second transistor configurable to conduct a sense current;
(h) a switched capacitor circuit coupled to the second transistor, the switched capacitor circuit configurable to generate a short detection voltage;
(i) a comparator having an output, a first comparator input, and a second comparator input, in which the first comparator input is coupled to the switched capacitor circuit, and the comparator is configurable to do a comparison of the short detection voltage with a short threshold voltage; and
(j) a controller coupled to the comparator and configurable to determine a fault status based on the comparison.
Claims 16, 17, and 21
(a) [claim 16] A system, comprising:
(b) [claim 16] a power terminal
(c) [claim 16] a load terminal; and
(d) [claim 16] an electronic fuse (EFUSE) circuit including:
(e) [claim 16] a first transistor configured to conduct a load current from the power terminal to the load terminal
(f) [claim 16] a switched load circuit coupled to the first transistor, the switched load circuit configured to switchably draw a test current; [claim 17] a current source configured to receive the test current; and a switch coupled between the first transistor and the current source
(g) [claim 16] a second transistor coupled to the first transistor, the second transistor configured to conduct a sense current, in which the sense current includes first and second portions, the first portion is representative of the load current, and the second portion is representative of the test current
(h) [claim 16] a switched capacitor circuit coupled to the second transistor, the switched capacitor circuit configured to generate a short detection voltage representative of the second portion
(i) [claim 16] a comparator having an output, a first comparator input, and a second comparator input, in which the first comparator input is coupled to the switched capacitor circuit, and the comparator is configured to compare the short detection voltage to a short threshold voltage
(j) [claim 21] the comparator includes a second input coupled to a reference voltage circuit, the reference voltage circuit configured to generate the short threshold voltage
As shown above, each limitation of claims 1-20 of the instant application is recited by, or is broader in scope than, a corresponding limitation of claims 1-21 of U.S. Patent No. 12,261,429. Where the instant claims omit a limitation of the patented claims, for example, the recitations in claim 20 of a switched load circuit configured to switchably draw a test current, of a sense current having first and second portions, and of a short detection voltage representative of the second portion, the omission of an element and its function is an obvious expedient. Where the instant claims recite a control circuit or a controller, the patented claims recite each switch as being configured to switchably connect its respective terminals, such that structure for controlling the recited switches is a necessary consequence of the patented claims, and the specification of U.S. Patent No. 12,261,429 may be referred to for the meaning of the terms used in the patented claims. Where the instant claims recite operational states or phases of the recited switches, such states are a selection among the switchable states already recited by the patented claims and would have been obvious to one having ordinary skill in the art. Further, a rearrangement of the ordinal labels applied to structurally identical switches, as in claims 3 and 4 of the instant application relative to claims 13 and 14 of U.S. Patent No. 12,261,429, does not render the claims patentably distinct. Claim 19 is treated as best understood in view of the rejection under 35 U.S.C. 112(b) set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shumkov et al. (US Patent Application Publication 2021/0175804 A1, hereinafter “Shumkov”) in view of Chauhan et al. (US Patent Application Publication 2018/0123578 A1, hereinafter “Chauhan”).
Regarding claim 11, Shumkov discloses (see Fig. 1 and Fig. 2A) a device (current sense circuit 200, implemented as the current sense circuit 120 of the switched mode power supply 100) comprising: a first transistor (FET 238; see [0034] of Shumkov “The FET 238 has a drain terminal coupled to the node 226, a source terminal coupled to the node 222, and a gate terminal”) coupled to a second transistor (replica FET 210; see [0033] of Shumkov “The replica FET 210 has a drain terminal coupled to the node 226, a source terminal coupled to a node 230, and a gate terminal”), wherein a second current through the second transistor is proportional to a first current through the first transistor (see [0039] of Shumkov “the replica FET 210 is a scaled replica of the FET 238 (e.g., N times smaller than the FET 238)”); a first current circuit (voltage controlled current source 216; see [0033] of Shumkov “The voltage controlled current source 216 has a first terminal coupled to a node 236, a second terminal coupled to the ground node 234, and a control terminal coupled to the node 232”) coupled to a first resistor (resistor 206; see [0033] of Shumkov “The resistor 206 is coupled between the node 224 and a node 228”; see [0033] of Shumkov “The amplifier 212 has a first input terminal (e.g., a non-inverting input terminal) coupled to the node 230, a second input terminal (e.g., an inverting input terminal) coupled to the node 228, and an output terminal coupled to a node 232”), wherein the first current circuit outputs a third current based on the second current (see [0038] of Shumkov “a current sunk by the voltage controlled current source 216 from the node 236 is approximately equal to a current flowing through the node 230”); a second current circuit (voltage controlled current source 214) coupled to the first transistor (see [0038] of Shumkov “the current of the voltage controlled current source 214, generated based on control of the voltage present at the node 232, is sunk from the node 226 through the replica FET 210”; Examiner’s Note: the node 226 is the drain terminal of the FET 238); a capacitor circuit (front end 121, comprising the capacitor 208, the switch 202, and the switch 204) coupled to the first current circuit and the first resistor (see [0033] of Shumkov “The capacitor 208 is coupled between the node 226 and the node 228”); and a control circuit (processing element 125) coupled to the capacitor circuit and the second current circuit (see [0026] of Shumkov “The processing element 125 further has one or more output terminals coupled to additional input terminals of the current sense circuit 120 (e.g., control terminals of switches of the current sense circuit 120, such as in the front end 121)”).
Shumkov does not disclose a comparator; and a control circuit coupled to the comparator.
However, Chauhan teaches (see Fig. 8 and Fig. 12) a comparator (fast trip comparator 813 of the sense path 803, having a first input coupled to the common node (A) and a second input coupled to the node (C) of a resistor divider; see [0061] of Chauhan “The fast trip comparator amplifier 813 compares the voltage at common node (A), which is the drain terminal for the transistors, to the voltage at node (C)”); and a control circuit (control IC 1201) coupled to the comparator (see [0075] of Chauhan “a control IC 1201 can include the operational amplifier, resistor divider circuitry, and a feedback FET device, the sense path devices as described hereinabove”; Examiner’s Note: the fast trip comparator amplifier 813 is one of the sense path devices described hereinabove, being disposed within the SENSE PATH 803 of Fig. 8).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Shumkov to include a comparator coupled to the capacitor circuit, and a control circuit coupled to the comparator, as taught by Chauhan, because it can help provide a fast trip output that quickly shuts down the power path when the load current rises faster than the sensing loop can respond (see [0056] of Chauhan “In a case where the load current suddenly increases, the circuits described hereinabove may not be fast enough to shut down the power transistor current conduction paths to prevent damage”; see [0057] of Chauhan “a fast trip output signal that can be used to quickly shut down the power path of the circuit”). Examiner’s Note: the capacitor 208 of the capacitor circuit of Shumkov is coupled to the node 226, which is the common drain node of the FET 238 and the replica FET 210, and which corresponds to the common node (A) that the fast trip comparator amplifier 813 of Chauhan monitors.
Regarding claim 12, Shumkov discloses (see Fig. 1 and Fig. 2A) wherein the third current is equal to the second current (see [0038] of Shumkov “a current sunk by the voltage controlled current source 216 from the node 236 is approximately equal to a current flowing through the node 230”; Examiner’s Note: the node 230 is the source terminal of the replica FET 210, such that the current sunk by the voltage controlled current source 216 is equal to the current conducted by the replica FET 210).
Allowable Subject Matter
Claims 1-10 and 20 would be allowable over the prior art of record if the nonstatutory double patenting rejection set forth in this Office action is overcome. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the control circuit is configurable to: enable the second transistor to receive the second current; enable the capacitor circuit to output a first voltage; receive a comparison of the first voltage and a reference voltage; and determine a fault condition based on the comparison.” Shumkov discloses a processing element 125 that controls the switches of the front end 121 to select between a sensing configuration and an averaging configuration, and the resulting output is used to generate a feedback voltage for regulating the output of the power converter (see [0029] of Shumkov “the feedback circuit 115 is configured to receive VREF and the output of the current sense circuit 120 and generate an error signal (ERROR) indicating a variation in VREF from VFB”), rather than to enable a second transistor to receive the current of the first transistor and to determine a fault condition from the resulting comparison.
Claims 2-10 would be allowable for the reasons given with respect to claim 1, from which they depend. Regarding claim 20, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “a switched capacitor circuit coupled to the second transistor, the switched capacitor circuit configurable to generate a short detection voltage”. Shumkov discloses a capacitor 208 that is charged during a sensing phase and that, during an averaging phase, discharges and forms a low-pass filter together with the resistor 206 (see [0037] of Shumkov “the capacitor 208 discharges to the node 226 and the resistor 206 and the capacitor 208 together form a low-pass filter”), which produces an averaged representation of the load current rather than a short detection voltage for comparison against a short threshold voltage, and Chauhan discloses no switched capacitor circuit.
Claims 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the nonstatutory double patenting rejection set forth in this Office action is overcome. Claim 19 would further require that the rejection under 35 U.S.C. 112(b) set forth above be overcome. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 13, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the second current circuit includes a fourth switch”. Shumkov discloses switches in the front end 121 whose control terminals are coupled to the processing element 125, but each voltage controlled current source of Shumkov is unswitched (see [0033] of Shumkov “The voltage controlled current source 214 has a first terminal coupled to the node 230, a second terminal coupled to the ground node 234, and a control terminal coupled to the node 232”), and Chauhan does not disclose a switch included in a current circuit coupled to the first transistor.
Claims 14-19 are objected to due to their dependency on claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 7,365,559 B2 discloses a current sensing power MOSFET in which a switched current source selectively supplies an additional current to the junction of a sense resistor and the mirror terminal, and the resulting change in the mirror terminal voltage is used to determine the load current.
US 11,595,034 B2 discloses a load switch having a current sense circuit that provides a sense current proportional to a load current conducted by a pass transistor, together with clamping circuitry that limits the sense voltage delivered to a controller.
US 11,362,504 B2 discloses an over-current sensing circuit in which a sense switch coupled in parallel with a load switch remains in an on state while the load switch is turned off responsive to a comparison of a voltage across the sense switch to a reference value.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838
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