Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1-2, 5, 11-13, is/are rejected under 35 U.S.C. 103 as being unpatentable over TOMISHIMA et al (Pub. No.: US 2021/0151437) in view of AAPA (Applicant Admitted Prior Art).
3. Regarding independent claim 1, TOMISHIMA et al teaches a 2T DRAM cell (Fig. 4, #400) with an parasitic capacitor (Fig. 4, between #444 to #443, paragraph [0021], lines 19-20), comprising: a write transistor (Fig. 4, #430) having one terminal connected to a write bit line (Fig. 4, BL_W 412) , the other terminal connected to a storage node (Fig. 4, SN 460), and a gate terminal (Fig.4, #434) connected to a write word line (Fig. 4, WL_W 424); a read transistor (Fig. 4, #440) having one terminal connected to a read bit line (Fig. 4, BL_R 414), the other terminal connected to a read word line (Fig. 4, WL_R 422), and a gate terminal (Fig. 4, #444) connected to the storage node (Fig. 4, SN 460); and a parasitic capacitor (Fig. 4, between #444 to #443, paragraph [0021], lines 19-20) formed between the gate terminal of the read transistor (Fig. 4, #440) and the other terminal of the read transistor (Fig. 4, #440) connected to the read word line (Fig. 4, WL_R 422).
TOMISHIMA et al is silent with respect to an asymmetric parasitic capacitor
AAPA teaches an asymmetric parasitic capacitor (see AAPA, paragraph [0004], lines 5-8).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of AAPA to the teaching of TOMISHIMA et al such that asymmetric parasitic capacitor has data retention time of at least several hours (see AAPA paragraph [0004], lines 12-13).
4. Regarding claim 2, TOMISHIMA et al teaches the parasitic capacitor (Fig. 4, between #444 to #443, paragraph [0021], lines 19-20) corresponds to an overlapping portion between the gate terminal (Fig. 4, #444) of the read transistor (Fig. 4, #440) and an active region of the read transistor (Fig. 4, #440) connected to the read word line (Fig. 4, WL_R 422).
TOMISHIMA et al is silent with respect to an asymmetric parasitic capacitor
AAPA teaches an asymmetric parasitic capacitor (see AAPA, paragraph [0004], lines 5-8).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of AAPA to the teaching of TOMISHIMA et al such that asymmetric parasitic capacitor has data retention time of at least several hours (see AAPA paragraph [0004], lines 12-13).
5. Regarding claim 5, TOMISHIMA et al teaches each of which is connected to a write word line (Fig. 4, WL_W 424), a write bit line (Fig. 4, BL_W 412), a read word line (Fig. 4, WL_R 422), and a read bit line (Fig. 4, BL_R 414),wherein when a read operation is performed on information stored in a selected 2T DRAM cell (Fig. 4, #400) among the plurality of 2T DRAM cells (Fig. 4, #400),a read transistor (Fig. 4, #440) of an unselected 2T DRAM cell (Fig. 4, #400) among the plurality of 2T DRAM cells (Fig. 4, #400) is always turned off by the parasitic capacitor (Fig. 4, between #444 to #443, paragraph [0021], lines 19-20) included in the 2T DRAM cell (Fig. 4, #400).
TOMISHIMA et al is silent with respect to an asymmetric parasitic capacitor
AAPA teaches an asymmetric parasitic capacitor (see AAPA, paragraph [0004], lines 5-8).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of AAPA to the teaching of TOMISHIMA et al such that asymmetric parasitic capacitor has data retention time of at least several hours (see AAPA paragraph [0004], lines 12-13).
6. Regarding claim 11, TOISHIMA et al teaches a parasitic capacitor (Fig. 4, between #444 to #443, paragraph [0021], lines 19-20) formed by the storage node (Fig. 4, SN 460) and the active region of the read transistor (Fig. 4, #440), which are formed in separate layers (see Fig. 4).
TOMISHIMA et al is silent with respect to an asymmetric parasitic capacitor
AAPA teaches an asymmetric parasitic capacitor (see AAPA, paragraph [0004], lines 5-8).
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of AAPA to the teaching of TOMISHIMA et al such that asymmetric parasitic capacitor has data retention time of at least several hours (see AAPA paragraph [0004], lines 12-13).
7. Regarding claim 12, TOMISHIMA et al teaches the insulating layer between the storage node (Fig. 4, SN 460) and the active region of the read transistor (Fig. 4, #440) formed on the same layer as the insulating layer (Fig. 7L, #742) between the gate of the read transistor (Fig. 4, #440) and the channel of the read transistor (Fig. 4, #440).
8. Regarding claim 13, TOMISHIMA et al teaches the insulating layer (Fig. 7L, #742) between the storage node (Fig. 4, SN 460) and the active region (Fig. 7L, between #724-#726) of the read transistor (Fig. 4, #440) formed of the same material as the insulating layer (Fig. 7L, #742) between the gate of the read transistor (Fig. 4, #440) and the channel of the read transistor (Fig. 4, #440).
Allowable Subject Matter
9. Claims 3-4, 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. With respect to claim 3, there is no teaching, suggestion, or motivation for combination in the prior art to an overlapping area between the gate terminal of the read transistor constituting the asymmetric parasitic capacitor and an active region of the read transistor connected to the read word line is wider than an overlapping area between the gate terminal of the read transistor and the active region of the read transistor connected to the read bit line.
11. With respect to claim 4, there is no teaching, suggestion, or motivation for combination in the prior art to a capacitance of the asymmetric parasitic capacitor is greater than a sum of a capacitance of a first parasitic capacitor formed between the gate terminal of the write transistor and the storage node and a capacitance of a second parasitic capacitor formed between the gate terminal of the read transistor and the storage node.
12. With respect to claim 6, there is no teaching, suggestion, or motivation for combination in the prior art to the selected 2T DRAM cell, a capacitance of the asymmetric parasitic capacitor is set to a value such that a voltage fluctuation rate of the storage node and a voltage fluctuation rate of the read word line have the same value.
13. With respect to claim 7, there is no teaching, suggestion, or motivation for combination in the prior art to a magnitude of a capacitance of the asymmetric parasitic capacitor is at least 1000 times larger than a sum of a capacitance of a first parasitic capacitor formed between the gate terminal of the write transistor and the storage node and a capacitance of a second parasitic capacitor formed between the gate terminal of the read transistor and the storage node.
14. With respect to claim 8, there is no teaching, suggestion, or motivation for combination in the prior art to in the unselected 2T DRAM cell, a voltage value fluctuation rate of the storage node is 0(zero).
15. With respect to claim 9, there is no teaching, suggestion, or motivation for combination in the prior art to a threshold voltage VTH of the read transistor, a voltage VSN(H) corresponding to a logic high stored in the storage node, a voltage VSH(L) corresponding to a logic low stored in the storage node, and a voltage VDD applied to a read word line connected to a selected 2T DRAM cell, when performing a read operation on information stored in the selected 2T DRAM cell satisfy the following Mathematical Formulas: VSN(L) <VTH- VDD < VSN(H) <VTH,and[VTH-VSN(H)]/VDDC<[VTH-VSN(L)]/VDD.
16. With respect to claim 10, there is no teaching, suggestion, or motivation for combination in the prior art to the asymmetric parasitic capacitor having a capacitance value proportional to the area of the overlapping portion between the storage node and the active region of the read transistor.
Conclusion
17. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, CHUNG (Pub. No: US 2025/0273261).
CHUNG (Pub. No: US 2025/0273261) shows 2T0C DRAM cells.
18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
08/21/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
Prosecution Insights