Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 10, 13, 15, & 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ro et al. PG Pub US 2024/0241828 A1 [hereinafter Ro] in view of Greathouse et al PG Pub US 2023/0132931 A1 [hereinafter Greathouse].
Regarding claims 1, 10, & 15, Ro discloses:
a cache memory (cache [0005]);
a non-volatile memory device (The processor may be further configured… to be a unit of moving the data related to the PIM operation to the memory [0006]); and
a processing device, comprising a data mover component configured to move data within the system, operatively coupled with the cache memory and the memory device, to perform operations comprising: receiving a first address corresponding to a physical memory region of the memory (The operations of the memory 120 that are controlled by the processor 110 may include general memory operations and PIM operations. The general memory operations may include the general operations of the memory 120 (e.g., read, write, copy, or erase) [0045]);
receiving a copy command from a host system, the copy command comprising a destination address in a storage region (a general non-PIM memory instruction may be a instruction that requests a general memory operation (e.g., read, write, copy, or erase [0087]);
responsive to determining that a cache line in the physical memory region is in a modified state (determine whether to move the data stored in the cache line to the memory based on determining whether the cache line state is a modified state [0008]), determining, using the destination address, a second address in the storage region of the memory device; and
responsive to determining that the first address and the second address are both within the system, storing, via a data mover transfer internal to the system performed by the data mover component, the cache line in the modified state and metadata associated with the cache line at the second address in the storage region (check a state of a cache line storing the data related to the PIM operation when performing the processing of the instruction causing the PIM operation, and determine whether to move the data stored in the cache line to the memory based on determining whether the cache line state is a modified state [0008]).
It is noted that Ro failed to explicitly disclose determining, using the destination address, a second address in the storage region of the memory device.
However, Greathouse discloses:
determining, using the destination address, a second address in the storage region of the memory device (The DMA command descriptors indicate, in various embodiments, a source address from which to read the data, a transfer size, and a destination address to which the data are to be written for each data transfer operation [0025]);
responsive to determining that the first address and the second address are both within the system, storing, via a data mover transfer internal to the system performed by the data mover component, the cache line in the modified state and metadata associated with the cache line at the second address in the storage region (the retrieved DMA job description 420 is a single transfer command to read data from physical addresses X and Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 (e.g., L3 or some last level cache) [0042]).
The systems of Ro and Greathouse are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Greathouse since this would enable the system of Ro to use a DMA to move data from the cache directly to the memory upon request. This system would enable “data transfer operations can be executed without delaying computation code, thus allowing communication and computation to overlap in time [0009].”
Regarding claims 5, 13, & 18, the limitations of these claims have been noted in the rejection of claims 1, 10, & 15. Ro also discloses:
wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the cache line (A tag 240 may include (i) a memory address 241 of data stored in its corresponding cache line and a state 243 of the cache line. For example, a tag's memory address may be an address where the data of a cache line corresponding to the memory address is stored in the memory. The state in the tag of a cache line may be set to different values to correspondingly indicate states such as: (1) a modified state in which the cache line is differentiated from a main storage device (e.g., the memory) with the cache line being modified and the data of the cache line exists in the cache only [0060]).
Claims 2, 4, 6-9, 12, 14, 17, 19, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ro in view of Greathouse further in view of Lee et al. PG Pub US 2023/0350832 A1 [hereinafter Lee].
Regarding claim 2, the limitations of this claim have been noted in the rejection of claim 1, it is noted that Ro failed to explicitly disclose:
wherein determining the second address further comprises looking up an address corresponding to the first address in a lookup table stored in a direct memory access (DMA) controller of the system.
However, Lee discloses:
wherein determining the second address further comprises looking up an address corresponding to the first address in a lookup table stored in a direct memory access (DMA) controller of the system (the CXL storage controller 111 of the CXL storage 110 may include a direct memory access (DMA) engine. The DMA engine included in the CXL storage controller 111 may transfer the map data MD present in the nonvolatile memory NVM to the CXL memory 120 without the interference or control of the host 101 [0100]).
The systems of Ro and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Lee since this would enable the memory of Ro to operate over a CXL switch. This system would improve the costs for new research and development [0005].
Regarding claims 4, 12, & 17, the limitations of these claims have been noted in the rejection of claims 1, 10, & 15, it is noted that Ro failed to explicitly disclose:
wherein the operations further comprise: sending a status message to the host system, the status message comprising at least one of a completion status or a session identifier of a logging session.
However, Lee discloses:
wherein the operations further comprise: sending a status message to a host processor, the status message comprising at least one of a completion status or a session identifier of a logging session (In operation PUP-S45, the CXL memory 120 may output, through the CXL memory interface circuit 121a, a write response REP_WR providing notification that the write request is completed [0090]).
The systems of Ro and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Lee since this would enable the memory of Ro to operate over a CXL switch. This system would improve the costs for new research and development [0005].
Regarding claims 6, 14, & 19, the limitations of these claims have been noted in the rejection of claims 1, 13, & 15, it is noted that Ro failed to explicitly disclose:
wherein the operations further comprise: storing a list comprising memory addresses associated with one or more modified cache lines, wherein the list is visible the host system (The storage controller includes a storage interface circuit that communicates with the host device through a compute express link (CXL) interface, a NAND interface circuit that communicates with the nonvolatile memory device, and a processor that loads map data from an external memory device placed outside the storage device through the storage interface circuit and controls the nonvolatile memory device through the NAND interface circuit based on the map data [0007]).
Regarding claim 7, the limitations of this claim have been noted in the rejection of claim 1, it is noted that Ro failed to explicitly disclose:
wherein the memory device comprises a computer express link (CXL) device and wherein the processing device is a direct memory access (DMA) controller of the system.
However, Lee discloses:
wherein the non-volatile memory device comprises a computer express link (CXL) device and wherein the processing device is a direct memory access (DMA) controller of the system (CXL storage controller 111 of the CXL storage 110 may include a direct memory access (DMA) engine [0100]).
The systems of Ro and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Lee since this would enable the memory of Ro to operate over a CXL switch. This system would improve the costs for new research and development [0005].
Regarding claims 8 & 20, the limitations of these claims have been noted in the rejection of claims 7 & 15, it is noted that Ro failed to explicitly disclose:
wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).
However, Lee discloses:
wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM) (the plurality of memory devices 102a and 102b may include a nonvolatile memory such as a flash memory, a phase change RAM (PRAM), a resistive RAM (RRAM), or a magnetic RAM (MRAM) [0033]).
The systems of Ro and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Lee since this would enable the memory of Ro to operate over a CXL switch. This system would improve the costs for new research and development [0005].
Regarding claim 9, the limitations of this claim have been noted in the rejection of claim 1, it is noted that Ro failed to explicitly disclose:
wherein the processing device is operatively coupled to the host system, and an interface between the host system and the processing device comprises a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.
However, Lee discloses:
wherein the processing device is operatively coupled to a host processor, and an interface between the host processor and the processing device comprises a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device (the computing system 100 may include a CXL switch SW_CXL, the host 101, the CXL storage 110, and the CXL memory 120 [0045]).
Claims 3 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ro in view of Boles PG Pub US 2023/0367712 A1 [hereinafter Boles].
Regarding claims 3 & 16, the limitations of these claims have been noted in the rejection of claims 1, Ro also discloses:
scanning the first address of the physical memory region; and responsive to determining that the cache line is in a further modified state, updating the cache line and metadata associated with the cache line in the storage region of the non-volatile memory device (check a state of a cache line storing the data related to the PIM operation when performing the processing of the instruction causing the PIM operation, and determine whether to move the data stored in the cache line to the memory based on determining whether the cache line state is a modified state [0008])
It is noted that Ro failed to explicitly disclose:
wherein the operations further comprise: receiving a synchronization request from the host system.
However, Boles discloses:
wherein the operations further comprise: receiving a synchronization request from a host processor (the memory device 320 may receive a synchronization request or message from the host system 310. [0051]).
The systems of Ro and Boles are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of “memory control.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the systems of Ro and Boles since this would enable the system of Ro to send synchronization commands to the memory. This system would improve memory coherence.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN D ROSSITER whose telephone number is (571)270-3788. The examiner can normally be reached M-F 8AM-4PM.
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/SEAN D ROSSITER/Primary Examiner, Art Unit 2133
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