DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 01/06/2026 has been considered by Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 20 of U.S. Patent No. 12,272,291 B1 in view of Kim et al (US 2019/0035322 A1). Although the claims at issue are not identical, they are not patentably distinct from each other. Shown below are the claims in which the underlined elements are the similar elements, while the italicized elements are the differences.
Application # 19/060540
US Patent # 12,272,291 B1
1. A gate driving circuit, comprising:
1. A gate driving circuit comprising a plurality of cascaded stage circuits,
wherein the each stage circuit comprises:
an input subcircuit configured to receive a start control signal and control a voltage potential of a second node;
an input subcircuit configured to receive a start signal or a stage transmission signal output by other stage circuits and configured to control a voltage of a second node;
an output subcircuit electrically connected to a third node and a fourth node, and configured to receive a first clock signal and output a gate driving signal according to a potential of the third node and a potential of the fourth node; and
a first output subcircuit configured to output a first gate driving signal according to a potential of a third node and a potential of a fourth node;
a second output subcircuit configured to output a second gate driving signal according to a potential of the second node;
a voltage stabilizing subcircuit electrically connected to a first power line, a second power line, the second node and the fourth node, and configured to receive a second clock signal different from the first clock signal and transmit a voltage on the first power line or a voltage on the second power line to the second node according to the second clock signal and the potential of the fourth node (A) in a low power consumption mode of the gate driving circuit.
a voltage stabilizing subcircuit electrically connected to a first power line and a second power line and configured to transmit a voltage on the first power line or a voltage on the second power line to the second node according to a voltage of the fourth node;
a first driving control subcircuit configured to control the voltage of the fourth node according to the voltage of the second node;
(A) wherein the voltage stabilizing subcircuit comprises a first transistor, a gate of the first transistor is configured to receive a clock signal, and an operation mode of the gate driving circuit comprises a low power consumption mode, when the gate driving circuit is in the low power consumption mode, the clock signal is a first voltage, and the first voltage turns on the first transistor.
As shown above, the Application claim 1 contains similar limitation to the US Patent, except for the output subcircuit configured to receive a first clock signal and the
a voltage stabilizing subcircuit configured to receive a second clock signal different from the first clock signal and transmit a voltage according to the second clock signal.
Kim (Fig. 1-10) discloses an output subcircuit (17; Fig. 5) electrically connected to a third node (Q; Fig. 5) and a fourth node (QB; Fig. 5), and configured to receive a first clock signal (CLK1; Fig. 5) and output a gate driving signal (Gout2; Fig. 5 and 6) according to (Paragraph [0089]) a potential of the third node (Q; Fig. 5) and a potential of the fourth node (QB; Fig. 5); and
a voltage stabilizing subcircuit (T7 and T6; Fig. 5) electrically connected to a first power line (VGH; Fig. 5) , the second node (QA; Fig. 5) and the fourth node (QB; Fig. 5), and configured to receive a second clock signal (G1CLK1; Fig. 5) different from the first clock signal (CLK1; Fig. 5 and 6; wherein figure shows clock signals G1CLK1 and CLK1 to be different clock signals) and transmit a voltage on the first power line (VGH; Fig. 5) according to (T6 and T7; Fig. 5) the second clock signal (G1CLK1; Fig. 5) and the potential of the fourth node (QB; Fig. 5) in a low power consumption mode (Fig. 6; wherein figure shows during step1 the output is disabled) of the gate driving circuit (Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify US Patent’s gate driving circuit by applying clock connections, as taught by Kim, so to use a gate driving circuit with clock connections for providing a gate driving circuit which, without using an inverter, supplies a gate voltage to a gate electrode of an n-type transistor or a p-type transistor in a display device including the n-type transistor and the p-type transistor (Paragraph [0010]).
With respect to dependent claims 2-19:
Claim 2 of Application is related to US Patent Claim 1.
Claim 3 of Application is related to US Patent Claim 3.
Claim 4 of Application is related to US Patent Claim 4.
Claim 5 of Application is related to US Patent Claim 5.
Claim 6 of Application is related to US Patent Claim 10.
Claim 7 of Application is related to US Patent Claim 11.
Claim 8 of Application is related to US Patent Claim 12.
Claim 9 of Application is related to US Patent Claim 13.
Claim 10 of Application is related to US Patent Claim 14.
Claim 11 of Application is related to US Patent Claim 15.
Claim 12 of Application is related to US Patent Claim 6.
Claim 13 of Application is related to US Patent Claim 7.
Claim 14 of Application is related to US Patent Claim 8.
Claim 15 of Application is related to US Patent Claim 9.
Claim 16 of Application is related to US Patent Claim 16.
Claim 17 of Application is related to US Patent Claim 17.
Claim 18 of Application is related to US Patent Claim 18.
Claim 19 of Application is not related to any claim of US Patent but is has been rejected in view of prior art reference of Zhang et al (CN 115578965 A) as shown below.
If Applicant agrees that there exists a Non-provisional Non-Statutory Double Patenting between the Application 19/060540 and US Patent 12,272,291 B1.
Then, the Examiner respectfully requests Applicant to provide a terminal disclaimer between Application and US Patent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0035322 A1) in view of Wei et al (US 2021/0407432 A1).
Claim 1, Kim (Fig. 1-10) discloses a gate driving circuit (Fig. 5; Paragraph [0091]), comprising:
an input subcircuit (T5; Fig. 5) configured to receive a start control signal (G1VST; Fig. 5; Paragraph [0079]; wherein discloses a first gate start voltage G1VST) and control a voltage potential (Paragraph [0114]) of a second node (QA; Fig. 5);
an output subcircuit (17; Fig. 5) electrically connected to a third node (Q; Fig. 5) and a fourth node (QB; Fig. 5), and configured to receive a first clock signal (CLK1; Fig. 5) and output a gate driving signal (Gout2; Fig. 5 and 6) according to (Paragraph [0089]) a potential of the third node (Q; Fig. 5) and a potential of the fourth node (QB; Fig. 5); and
a voltage stabilizing subcircuit (T7 and T6; Fig. 5) electrically connected to a first power line (VGH; Fig. 5) , the second node (QA; Fig. 5) and the fourth node (QB; Fig. 5), and configured to receive a second clock signal (G1CLK1; Fig. 5) different from the first clock signal (CLK1; Fig. 5 and 6; wherein figure shows clock signals G1CLK1 and CLK1 to be different clock signals) and transmit a voltage on the first power line (VGH; Fig. 5) according to (T6 and T7; Fig. 5) the second clock signal (G1CLK1; Fig. 5) and the potential of the fourth node (QB; Fig. 5) in a low power consumption mode (Fig. 6; wherein figure shows during step1 the output is disabled) of the gate driving circuit (Fig. 5).
Kim does not expressly disclose a voltage stabilizing subcircuit electrically connected to a first power line, a second power line, the second node and the fourth node, and transmit a voltage on the first power line or a voltage on the second power line to the second node the potential of the fourth node in a low power consumption mode of the gate driving circuit.
Wei (Fig. 1-8) discloses a voltage stabilizing subcircuit (M2-M4; Fig. 3) electrically connected to a first power line (VGH; Fig. 3), a second power line (VGL; Fig. 3), the second node (PU; Fig. 3) and the fourth node (PD; Fig. 3), and transmit a voltage on the first power line (VGH; Fig. 3) or a voltage on the second power line (VGL; Fig. 3) to the second node (PU; Fig. 3) the potential of the fourth node (PD; Fig. 3) in a low power consumption mode (Paragraph [0031]) of the gate driving circuit (Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s gate driving circuit by applying a regulating circuit, as taught by Wei, so to use a gate driving circuit with a regulating circuit for regulating a leakage current of the enable signal generation circuit based on the second voltage signal, so that the leakage current of the enable signal generation circuit is reduced, thereby keeping the enable signal generated by the enable signal generation circuit stable (Paragraph [0006]).
Claim 20, Kim (Fig. 1-10) discloses a display panel (Fig. 1) comprising a gate driving circuit (Fig. 5; Paragraph [0091]), wherein the gate driving circuit (Fig. 5; Paragraph [0091]), comprises:
an input subcircuit (T5; Fig. 5) configured to receive a start control signal (G1VST; Fig. 5; Paragraph [0079]; wherein discloses a first gate start voltage G1VST) and control a voltage potential (Paragraph [0114]) of a second node (QA; Fig. 5);
an output subcircuit (17; Fig. 5) electrically connected to a third node (Q; Fig. 5) and a fourth node (QB; Fig. 5), and configured to receive a first clock signal (CLK1; Fig. 5) and output a gate driving signal (Gout2; Fig. 5 and 6) according to (Paragraph [0089]) a potential of the third node (Q; Fig. 5) and a potential of the fourth node (QB; Fig. 5); and
a voltage stabilizing subcircuit (T7 and T6; Fig. 5) electrically connected to a first power line (VGH; Fig. 5) , the second node (QA; Fig. 5) and the fourth node (QB; Fig. 5), and configured to receive a second clock signal (G1CLK1; Fig. 5) different from the first clock signal (CLK1; Fig. 5 and 6; wherein figure shows clock signals G1CLK1 and CLK1 to be different clock signals) and transmit a voltage on the first power line (VGH; Fig. 5) according to (T6 and T7; Fig. 5) the second clock signal (G1CLK1; Fig. 5) and the potential of the fourth node (QB; Fig. 5) in a low power consumption mode (Fig. 6; wherein figure shows during step1 the output is disabled) of the gate driving circuit (Fig. 5).
Kim does not expressly disclose a voltage stabilizing subcircuit electrically connected to a first power line, a second power line, the second node and the fourth node, and transmit a voltage on the first power line or a voltage on the second power line to the second node the potential of the fourth node in a low power consumption mode of the gate driving circuit.
Wei (Fig. 1-8) discloses a voltage stabilizing subcircuit (M2-M4; Fig. 3) electrically connected to a first power line (VGH; Fig. 3), a second power line (VGL; Fig. 3), the second node (PU; Fig. 3) and the fourth node (PD; Fig. 3), and transmit a voltage on the first power line (VGH; Fig. 3) or a voltage on the second power line (VGL; Fig. 3) to the second node (PU; Fig. 3) the potential of the fourth node (PD; Fig. 3) in a low power consumption mode (Paragraph [0031]) of the gate driving circuit (Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s gate driving circuit by applying a regulating circuit, as taught by Wei, so to use a gate driving circuit with a regulating circuit for regulating a leakage current of the enable signal generation circuit based on the second voltage signal, so that the leakage current of the enable signal generation circuit is reduced, thereby keeping the enable signal generated by the enable signal generation circuit stable (Paragraph [0006]).
Claim 2, Kim (Fig. 1-10) discloses wherein the voltage stabilizing subcircuit (T7 and T6; Fig. 5) comprises a first transistor (T6; Fig. 5) having a gate configured to receive the second clock signal (G1CLK1; Fig. 5), and the voltage of the first power line (VGH; Fig. 5) is transmitted to the second node (QA; Fig. 5) when the second clock signal turns on (Step1; Fig. 6) the first transistor (T6; Fig. 5).
Claim 4, Kim (Fig. 1-10) discloses wherein the voltage stabilizing subcircuit (T7 and T6; Fig. 5) further comprises a second transistor (T7; Fig. 5), a gate of the second transistor (T7; Fig. 5) is electrically connected to the fourth node (QB; Fig. 5), one of a source and a drain of the second transistor (T7; Fig. 5) is electrically connected to the first power line (VGH; Fig. 5), another one of the source and the drain of the second transistor (T7; Fig. 5) is electrically connected to one of a source and a drain of the first transistor (T6; Fig. 5), and another one of the source and the drain of the first transistor (T6; Fig. 5) is electrically connected to the second node (QA; Fig. 5).
Claim 5, Kim (Fig. 1-10) discloses wherein the voltage on the first power line (VGH; Fig. 5) is transmitted to the one of the source and the drain of the first transistor (T6; Fig. 5) when (Step1; Fig. 6) a voltage the potential of the fourth node (QB; Fig. 5) turns on the second transistor (T7; Fig. 5).
Claim 6, Wei (Fig. 1-8) discloses wherein the voltage stabilizing subcircuit (13; Fig. 3) further comprises a third transistor (M3; Fig. 3), one of a source and a drain of the third transistor (M3; Fig. 3) is electrically connected to the second power line (VGL; Fig. 3), another one of the source and the drain of the third transistor (M3; Fig. 3) is electrically connected (Fig. 3; wherein connected to node PU through the enabled transistor M4) to the second node (PU; Fig. 3), and a gate of the third transistor (M3; Fig. 3) is electrically connected to the fourth node (PD; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s gate driving circuit by applying a regulating circuit, as taught by Wei, so to use a gate driving circuit with a regulating circuit for regulating a leakage current of the enable signal generation circuit based on the second voltage signal, so that the leakage current of the enable signal generation circuit is reduced, thereby keeping the enable signal generated by the enable signal generation circuit stable (Paragraph [0006]).
Claim 7, Wei (Fig. 1-8) discloses wherein the voltage on the second power line (VGL; Fig. 3) is transmitted to the second node (PU; Fig. 3) when a voltage the potential of the fourth node (PD; Fig. 3) turns on the third transistor (M3; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s gate driving circuit by applying a regulating circuit, as taught by Wei, so to use a gate driving circuit with a regulating circuit for regulating a leakage current of the enable signal generation circuit based on the second voltage signal, so that the leakage current of the enable signal generation circuit is reduced, thereby keeping the enable signal generated by the enable signal generation circuit stable (Paragraph [0006]).
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0035322 A1) in view of Wei et al (US 2021/0407432 A1) as applied to claims 2 and 6 above, and further in view of Shang et al (US 2022/0051608 A1).
Claim 3, Kim in view of Wei discloses the gate driving circuit according to claim 2.
Kim in view of Wei does not expressly disclose wherein the first transistor is a dual-gate indium gallium zinc oxide thin film transistor having a first gate and a second gate that are configured to receive the second clock signal.
Shang (Fig. 15) discloses wherein the first transistor (T10; Fig. 15) is a dual-gate indium gallium zinc oxide thin film transistor (Paragraph [0096]; wherein discloses “The active layer 24 may be made of amorphous indium gallium zinc oxide (a-IGZO)”) having a first gate and a second gate that are configured to receive the second clock signal (Fig. 15 and 12; wherein figure shows transistor T10 which is a double gate transistor that has both gate electrodes are connected to a clock signal CLK2) .
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a dual-gate transistor, as taught by Shang, so to use a gate driving circuit with a dual-gate transistor for providing the decrease of the leakage of the thin film transistor, and the driving capability can be improved (Paragraph [0098]).
Claim 8, Kim in view of Wei discloses the gate driving circuit according to claim 6.
Kim in view of Wei does not expressly disclose wherein the third transistor is a dual-gate indium gallium zinc oxide thin film transistor having a first gate and a second gate that are electrically connected to the fourth node.
Shang (Fig. 15) discloses wherein the third transistor (Fig. 7 and 15; wherein the difference between embodiments is that figure 7 shows all the transistors are a single gate transistor structure whereas figure 15 shows all the transistors are double gate transistors; therefore with this teaching in mind it would have been obvious to apply a double gate structure to any shift register circuit to reduce current leakage within the circuit; therefore by applying the double gate structure to Wei’s transistor T3 would have be obvious in view of Shang’s teaching) is a dual-gate indium gallium zinc oxide thin film transistor (Paragraph [0096]; wherein discloses “The active layer 24 may be made of amorphous indium gallium zinc oxide (a-IGZO)”) having a first gate and a second gate that are electrically connected to the fourth node (Fig. 7 and 15; wherein the difference between embodiments is that figure 7 shows all the transistors are a single gate transistor structure whereas figure 15 shows all the transistors are double gate transistors; therefore with this teaching in mind it would have been obvious to apply a double gate structure to any shift register circuit to reduce current leakage within the circuit; Shang clearly shows that all the double gate transistors have gate electrodes connected to the same element, therefore by applying the double gate structure to Wei’s transistor T3 would have be obvious in view of Shang’s teaching).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a dual-gate transistor, as taught by Shang, so to use a gate driving circuit with a dual-gate transistor for providing the decrease of the leakage of the thin film transistor, and the driving capability can be improved (Paragraph [0098]).
Claims 9-11 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0035322 A1) in view of Wei et al (US 2021/0407432 A1) as applied to claim 1 above, and further in view of Zhang et al (CN 115578965 A).
Claim 9, Kim in view of Wei discloses the gate driving circuit according to claim 1.
Kim in view of Wei does not expressly disclose further comprising a reset subcircuit configured to control the potential of the second node according to a reset signal.
Zhang (Fig. 1-15) discloses further comprising a reset subcircuit (600; Fig. 14; wherein discloses a reset module) configured to control the potential of the second node (N1; Fig. 14) according to a reset signal (RST; Fig. 14).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a reset module, as taught by Zhang, so to use a gate driving circuit with a reset module for avoiding the influence of the previous frame display picture on the current one frame display picture, so as to improve the display effect (See page 16 of translation).
Claim 10, Zhang (Fig. 1-15) discloses wherein the reset subcircuit (600; Fig. 14) comprises a fourth transistor (T11; Fig. 14), one of a source and a drain of the fourth transistor (T11; Fig. 14) is electrically connected to the first power line (VGH; Fig. 14), another one of the source and the drain of the fourth transistor (T11; Fig. 14) is electrically connected to the second node (N1; Fig. 14), and a gate of the fourth transistor (T11; Fig. 14) is configured to receive the reset signal (RST; Fig. 14).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a reset module, as taught by Zhang, so to use a gate driving circuit with a reset module for avoiding the influence of the previous frame display picture on the current one frame display picture, so as to improve the display effect (See page 16 of translation).
Claim 11, Zhang (Fig. 1-15) discloses wherein in a first frame of operation (See page 16 of translation; wherein discloses “ the reset module 600 at the starting time of a frame display picture is in the on state, the second level signal Vgh is transmitted to the second node N2”) of the gate driving circuit (Fig. 14), the reset signal (RST; Fig. 14) turns on the fourth transistor (T11; Fig. 14) before a pulse of the start control signal (IN; Fig. 14), such that the voltage on the first power line (VGH; Fig. 14) is transmitted to the second node (N1; Fig. 14).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a reset module, as taught by Zhang, so to use a gate driving circuit with a reset module for avoiding the influence of the previous frame display picture on the current one frame display picture, so as to improve the display effect (See page 16 of translation).
Claim 16, Kim in view of Wei discloses the gate driving circuit according to claim 1.
Kim in view of Wei does not expressly disclose further comprising:
a second driving control subcircuit electrically connected between the second node and the third node and having a control terminal electrically connected to a driving control line, wherein the second driving control subcircuit is configured to control a conduction between the second node and the third node.
Zhang (Fig. 1-15) discloses further comprising:
a second driving control subcircuit (300; Fig. 4; wherein discloses a voltage isolation module) electrically connected between the second node (N1; Fig. 4) and the third node (N2; Fig. 4) and having a control terminal (300; Fig. 4) electrically connected to a driving control line (CKN; Fig. 4), wherein the second driving control subcircuit (300; Fig. 4) is configured to control a conduction (See page 5 of translation: wherein discloses “the isolation module 300 is respectively electrically connected with the first node N1, the second node N2 and the voltage stabilizing control end CKN, the voltage stabilizing control signal ckn and the potential of the first node N1 according to the voltage stabilizing control end CKN, controlling the potential of the second node N2”) between the second node (N1; Fig. 4) and the third node (N2; Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a voltage isolation module, as taught by Zhang, so to use a gate driving circuit with a voltage isolation module for providing the first driving mode, driving the display panel with a lower driving frequency, the display picture can be maintained as a standby picture, so as to reduce the power consumption of the display panel (See page 6 of translation).
Claim 17, Zhang (Fig. 1-15) discloses wherein the second driving control subcircuit (300; Fig. 4) is configured to eliminate a first pulse (Fig. 2; wherein prior to t20 and after t21) at the second node (N1; Fig. 4) in a frame (t2; Fig. 2) and retain a second pulse (t21; Fig. 2) at the second node (N2; Fig. 4) in the frame (t2; Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a voltage isolation module, as taught by Zhang, so to use a gate driving circuit with a voltage isolation module for providing the first driving mode, driving the display panel with a lower driving frequency, the display picture can be maintained as a standby picture, so as to reduce the power consumption of the display panel (See page 6 of translation).
Claim 18, Zhang (Fig. 1-15) discloses wherein the second driving control subcircuit (300; Fig. 4) comprises a transistor (T3; Fig. 4), one of a source and a drain of the transistor (T3; Fig. 4) is electrically connected to an output terminal of the input subcircuit (110/100; Fig. 4), another one of the source and the drain of the transistor (T3; Fig. 4) is electrically connected to the third node (N2; Fig. 4), and a gate of the transistor (T3; Fig. 4) is electrically connected to the driving control line (CKN; Fig. 4),
wherein the second node (N1; Fig. 4) and the third node (N2; Fig. 4) is conducting (See page 5 of translation: wherein discloses “the isolation module 300 is respectively electrically connected with the first node N1, the second node N2 and the voltage stabilizing control end CKN, the voltage stabilizing control signal ckn and the potential of the first node N1 according to the voltage stabilizing control end CKN, controlling the potential of the second node N2”) when the transistor turns on (T3; Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a voltage isolation module, as taught by Zhang, so to use a gate driving circuit with a voltage isolation module for providing the first driving mode, driving the display panel with a lower driving frequency, the display picture can be maintained as a standby picture, so as to reduce the power consumption of the display panel (See page 6 of translation).
Claim 19, Zhang (Fig. 1-15) discloses wherein the second driving control subcircuit (300; Fig. 9) further comprises an anti-leakage transistor (T6; Fig. 9), one of a source and a drain of the anti-leakage transistor (T6; Fig. 9) is electrically connected to the another one of the source and the drain of the transistor (T3; Fig. 9), another one of the source and the drain of the anti-leakage transistor (T6; Fig. 9) is electrically connected to the third node (N2; Fig. 9), and a gate of the anti-leakage transistor (T6; Fig. 9) is electrically connected to an anti-leakage signal line (VGL; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying a voltage isolation module, as taught by Zhang, so to use a gate driving circuit with a voltage isolation module for providing the first driving mode, driving the display panel with a lower driving frequency, the display picture can be maintained as a standby picture, so as to reduce the power consumption of the display panel (See page 6 of translation).
Claims 12-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0035322 A1) in view of Wei et al (US 2021/0407432 A1) as applied to claim 1 above, and further in view of Yamamoto (US 2022/0392403 A1).
Claim 12, Kim in view of Wei discloses the gate driving circuit according to claim 1.
Kim in view of Wei does not expressly disclose further comprising:
a first driving control subcircuit electrically connected to the second node and the fourth node, and configured to output a voltage potential inverted with the voltage potential of the second node to the fourth node.
Yamamoto (Fig. 1-28) discloses further comprising:
a first driving control subcircuit (321; Fig. 18) electrically connected to the second node (N1; Fig. 18) and the fourth node (OUT1; Fig. 18), and configured to output a voltage potential inverted (OUT1; Fig. 19) with the voltage potential of the second node (N1; Fig. 19) to the fourth node (OUT1; Fig. 19).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying an inverter circuit, as taught by Yamamoto, so to use a gate driving circuit with an inverter circuit for providing a display device (e.g., an organic EL display device) that includes pixel circuits, in each of which an N-type transistor and a P-type transistor coexist, and that operates normally, while suppressing an increase in processing cost (Paragraph [0114]).
Claim 13, Yamamoto (Fig. 1-28) discloses wherein the first driving control subcircuit (321; Fig. 18) comprises:
a fifth transistor (M4; Fig. 18), one of a source and a drain of the fifth transistor (M4; Fig. 18) is electrically connected to the first power line (VGH; Fig. 18), another one of the source and the drain of the fifth transistor (M4; Fig. 18) is electrically connected to the fourth node (OUT1; Fig 18), and a gate of the fifth transistor (M4; Fig. 18) is electrically connected to the second node (N1; Fig. 18); and
a sixth transistor (M5; Fig. 18), one of a source and a drain of the sixth transistor (M5; Fig. 18) is electrically connected to a third power line (VGL; Fig. 18), another one of the source and the drain of the sixth transistor (M5; Fig. 18) is electrically connected to the fourth node (OUT1; Fig. 18), and a gate of the sixth transistor (M5; Fig. 18) is electrically connected to the second node (N1; Fig. 18),
wherein the fifth transistor (M4; Fig. 18) and the sixth transistor (M5; Fig. 18) have different channel types (Paragraph [0199]; wherein discloses “The first output circuit 321 includes a P-type transistor M4 and an N-type transistor M5”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying an inverter circuit, as taught by Yamamoto, so to use a gate driving circuit with an inverter circuit for providing a display device (e.g., an organic EL display device) that includes pixel circuits, in each of which an N-type transistor and a P-type transistor coexist, and that operates normally, while suppressing an increase in processing cost (Paragraph [0114]).
Claim 15, Yamamoto (Fig. 1-28) discloses wherein a voltage on the third power line (VGL; Fig. 18) is transmitted to the fourth node (OUT1; Fig. 18) when the voltage potential of the second node (N1; Fig. 18; Paragraph [0179]; wherein discloses “Hence, the potentials at the first internal node N1 and the second internal node N2 increase to high level, and the transistor M1 and the transistor M4 go into off state and the transistor M5 goes into on state. By the transistor M4 going into off state and the transistor M5 going into on state, the output signal OUT1 changes from high level to low level”) turns on the sixth transistor (M5; Fig. 18).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Wei’s gate driving circuit by applying an inverter circuit, as taught by Yamamoto, so to use a gate driving circuit with an inverter circuit for providing a display device (e.g., an organic EL display device) that includes pixel circuits, in each of which an N-type transistor and a P-type transistor coexist, and that operates normally, while suppressing an increase in processing cost (Paragraph [0114]).
Claims 3, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2019/0035322 A1) in view of Wei et al (US 2021/0407432 A1) and Yamamoto (US 2022/0392403 A1) as applied to claim 13 above, and further in view of Shang et al (US 2022/0051608 A1).
Claim 14, Liu in view of Wei and Yamamoto discloses the gate driving circuit according to claim 13.
Liu in view of Wei and Yamamoto does not expressly disclose wherein the sixth transistor is a double-gate transistor having a first gate and a second gate that are electrically connected to the second node.
Shang (Fig. 15) discloses wherein the sixth transistor (Fig. 7 and 15; wherein the difference between embodiments is that figure 7 shows all the transistors are a single gate transistor structure whereas figure 15 shows all the transistors are double gate transistors; therefore with this teaching in mind it would have been obvious to apply a double gate structure to any shift register circuit to reduce current leakage within the circuit; therefore by applying the double gate structure to Liu’s transistor T1 would have be obvious in view of Shang’s teaching) is a double-gate transistor (Paragraph [0096]; wherein discloses “The active layer 24 may be made of amorphous indium gallium zinc oxide (a-IGZO)”) having a first gate and a second gate that are electrically connected to the second node (Fig. 7 and 15; wherein the difference between embodiments is that figure 7 shows all the transistors are a single gate transistor structure whereas figure 15 shows all the transistors are double gate transistors; therefore with this teaching in mind it would have been obvious to apply a double gate structure to any shift register circuit to reduce current leakage within the circuit; Shang clearly shows that all the double gate transistors have gate electrodes connected to the same element, therefore by applying the double gate structure to Liu’s transistor T1 would have be obvious in view of Shang’s teaching).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Liu in view of Wei and Yamamoto’s gate driving circuit by applying a dual-gate transistor, as taught by Shang, so to use a gate driving circuit with a dual-gate transistor for providing the decrease of the leakage of the thin film transistor, and the driving capability can be improved (Paragraph [0098]).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Kim et al (US 2019/0035322 A1), Wei et al (US 2021/0407432 A1), Zhang et al (CN 115578965 A), Yamamoto (US 2022/0392403 A1), and Shang et al (US 2022/0051608 A1) have been used for new ground rejection.
Claims 1 and 20 are rejected in view of newly discovered reference(s) to Kim et al (US 2019/0035322 A1) and Wei et al (US 2021/0407432 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 03/17/2026