Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/23/2026 have been fully considered but they are not persuasive for the following reasons, and also moot in view of the new grounds of rejection (see below).
Specifically, Applicant argues on pg. 8:
“According to implementations of these features, the set board provides the control command signal through the second interface circuit to the first timing controller, the plurality of timing controllers execute the target operation corresponding to the control command signal through the first interface circuit, and the set board transfers image data to the plurality of the timing controllers through the fourth interface circuit implemented based on a V-by-One scheme.
Furthermore, the fourth interface circuit for transferring the image data to the plurality of timing controller is separated from the first interface circuit for providing the control command signal…”.
Examiner responds that claim 1 does not indicate that the newly introduced fourth interface circuit is separated from the first interface circuit. The claim merely states a function of the fourth interface circuit. Therefore, this argument is rendered unpersuasive. Also, a third interface has not been introduced into the subject matter of claim 1, which introduces unclear subject matter (see rejection below). Appropriate correction is required.
Applicant continues on pg. 8:
“The Office has not established a prima facie case of anticipation or obviousness for at least the features of "a plurality of timing controllers being connected to one another through a first interface circuit based on a serial communication scheme, for executing a target operation corresponding to the control command signal" and "wherein the set board transfers image data to the plurality of timing controllers through a fourth interface circuit implemented based on a V- by-One scheme" as recited in amended claim 1.
Yang discloses that the source controller 100 (corresponding to the set board in claim 1) sends the video data and related commands through the high-speed transmission interface of the forward channels in paragraph [0036].
However, Yang does not distinguish the interface for transferring video data from the interface for providing related commands. In general, Yang does not disclose or suggest the features of "a plurality of timing controllers being connected to one another through a first interface circuit based on a serial communication scheme, for executing a target operation corresponding to the control command signal" and "wherein the set board transfers image data to the plurality of timing controllers through a fourth interface circuit implemented based on a V- by-One scheme" as recited in amended claim 1.
Kim relates to transmission of image data using the High-Definition Multimedia Interface (HDMI) in which image data and control data are packetized and transmitted together.
However, Kim does not distinguish the interface for transferring image data from the interface for providing control data. In general, Kim does not disclose or suggest the features of "a plurality of timing controllers being connected to one another through a first interface circuit based on a serial communication scheme, for executing a target operation corresponding to the control command signal" and "wherein the set board transfers image data to the plurality of timing controllers through a fourth interface circuit implemented based on a V-by-One scheme" as recited in amended claim 1, and fails to remedy the deficiencies of Yang.
For at least these reasons, the Office has not established a prima facie case of anticipation or obviousness for all of the features recited in amended claim 1. Accordingly, Applicant requests reconsideration and withdrawal of the rejections and submits that all claims are in condition for allowance.”
Examiner directs Applicant to the new grounds of rejection (see below).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 13 and 15 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim1 recites the limitation "a fourth interface circuit". There is insufficient antecedent basis for this limitation in the claim since no third interface circuit has been introduced. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6,16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US Pub. No. 2023/0171374 A1).
As to claim 1, Yang shows a tiling (i.e. splicing) display apparatus (Fig. 1 and para. 34) comprising: a set board (source controller 100), configured to generate a control command signal (Fig. 1 and paras. 35 and 36); and a plurality of display modules (i.e. serial unit, Fig. 1 and para. 31) each of which comprises a timing controller (i.e. clock processing circuit 306/406 and/or command processing circuit 304/404, Figs. 3 and 4 and paras. 45 and 46), a plurality of timing controllers are connected to one another through a first interface circuit based on a serial communication scheme (Figs. 1 – 4 and paras. 45 and 46) for executing a target operation corresponding to the control command signal (Figs. 3 and 4 and paras. 32, 45 and 46), wherein, each display module comprises a display panel based on a micro light emitting diode on which a pixel array is disposed (Fig. 1 and para. 31), each pixel in the pixel array comprising a micro-light emitting diode chip (inherently included in any LED, Fig. 1 and para. 31) , wherein the first interface circuit is implemented with a bidirectional serial interface having a feedback loop type between adjacent timing controllers (Figs. 1 and 3 and paras. 35 and 38), and wherein the set board is connected to a first timing controller in a first display module through a second interface circuit (Figs. 1, 3 and 4 and paras. 32, 45 and 46) and provides the control command signal to the first timing controller (Figs. 1, 3 and 4 and paras. 32, 45 and 46), wherein the set board transfers image data to the plurality of timing controllers through an interface circuit implemented based on a V-by-One scheme (Fig. 1 and para. 36).
As to claim 2, Yang shows that the timing controller comprises a mode (i.e. bypass) selector (Fig. 3 and para. 45), and the set board is further configured to control the mode selector to activate a bypass communication mode (Fig. 3 and para. 45).
As to claim 3, Yang shows that the control command signal is transferred to a target timing controller on the basis of a bypass scheme through a serial interface in a first direction to cause the target timing controller to execute the target operation (Figs. 3 and 4 and paras. 45 and 46), where in the bypass scheme, the control command signal passes through a timing controller previous to the target timing controller in a signal transferring direction, the first direction indicating a direction from the set board to the display module (Figs. 3 and 4 and paras. 45 and 46).
As to claim 4, Yang shows that the target timing controller generates a control response signal corresponding to the control command signal (Figs. 3 and 4 and paras. 45 and 46), and feedbacks the control response signal to the first timing controller serving as the target timing controller, on the basis of the bypass scheme through a serial interface in a second direction opposite to the first direction (Figs. 3 and 4 and paras. 45 and 46).
As to claim 5, Yang shows that the control command signal comprises: a header region including a command signal representing a kind of a control command and position information about a display module corresponding to the target timing controller (inherently the case, Fig. 7 and paras. 52 and 56); a data region including control command data; and an information region including a check flag signal for transmission/reception error check (Fig. 7 and para. 52).
As to claim 6, Yang shows that the control command signal passes through a certain timing controller previous to the target timing controller in the first direction (para. 38), the timing controller analyzes only the header region while transferring the control command signal to a subsequent timing controller in the first direction (para. 56).
As to claim 16, Yang shows that wherein the tiling display apparatus operates in a bypass communication mode (Fig. 3 and para. 45), and in one bypass communication, one of the plurality of timing controllers is taken as the target timing controller (Figs. 3, 4 and 7 and paras. 45, 46, 52 and 56).
As to claim 20, Yang shows that the first interface circuit includes a first transmission cable (i.e. first interface between source controller and first serial unit, Figs. 1, 3 and 4 and paras. 32, 45 and 46), and the fourth interface circuit includes a separate transmission cable physically separated from the first transmission cable (i.e. any other feed forward interface, Figs. 1, 3 and 4 and paras. 32, 45 and 46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kim et al. (US Pub. No. 2018/0165051 A1).
As to claim 17, Yang shows that the second interface circuit is implemented with a unidirectional serial interface or the bidirectional serial interface (para. 38).
Yang does not show that the bidirectional serial interface is implemented as a dual serial peripheral interface (SPI), and the unidirectional serial interface is implemented as a single SPI.
Kim shows that a bidirectional serial interface is implemented as a dual serial peripheral interface (SPI) (i.e. HDMI), and a unidirectional serial interface is implemented as a single (i.e. HDMI, Fig. 4 and paras. 74 – 92).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the teachings of Yang with those of Kim because designing the system in this way allows the device to perform error detection (para. 80).
Allowable Subject Matter
Claims 7 – 15, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites that “… the control response signal comprises: a header region including position information about the first timing controller and information representing whether the command signal is normal; a data region including control execution data; and an information region including a check flag signal for transmission/reception error check.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 8 contains allowable subject matter at least by virtue of its dependence on claim 7.
Claim 9 recites that “…that the tiling display apparatus operates in an asynchronous overlap communication mode, each of the plurality of timing controllers is the target timing controller, and wherein each timing controller analyzes the header region and stores the control command data in a target memory while transferring the control command signal to a subsequent timing controller in the first direction.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 10 contains allowable subject matter at least by virtue of its dependence on claim 9.
Claim 11 recites that “…the tiling display apparatus operates in the synchronous overlap communication mode, each of the plurality of timing controllers is the target timing controller, and wherein each timing controller analyzes the header region and stores the control command data in a temporary buffer while transferring the control command signal to a subsequent timing controller in the first direction.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claims 12 – 15 contain allowable subject matter at least by virtue of their dependence on claim 11.
Claim 18 recites that “…the timing controller further comprises a multiplexer, a controller, and a temporary buffer that is activated in the synchronous overlap communication mode and is deactivated in the other communication modes.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 19 recites that “…the micro-light emitting diode chip is transferred from R/G/B donors and is mounted on a thin film transistor backplane.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CARL ADAMS/Examiner, Art Unit 2627