Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/16/2026 have been fully considered but they are moot in view of the new grounds of rejection (see below).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 13 and 15 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim1 recites the limitation “the first interface circuit card". There is insufficient antecedent basis for this limitation in the claim since no third interface circuit has been introduced. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 6,16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang.
Claims 1 – 6, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Pub. No. 2023/0171374 A1) in view of Jeong et al. (US Pub. No. 2021/0365082 A1).
As to claim 1, Yang shows a tiling (i.e. splicing) display apparatus (Fig. 1 and para. 34) comprising: a set board (source controller 100), configured to generate a control command signal (Fig. 1 and paras. 35 and 36); and a plurality of display modules (i.e. serial unit, Fig. 1 and para. 31) each of which comprises a timing controller (i.e. clock processing circuit 306/406 and/or command processing circuit 304/404, Figs. 3 and 4 and paras. 45 and 46), a plurality of timing controllers are connected to one another through a first interface circuit based on a serial communication scheme (Figs. 1 – 4 and paras. 45 and 46) for executing a target operation corresponding to the control command signal (Figs. 3 and 4 and paras. 32, 45 and 46), wherein, each display module comprises a display panel based on a micro light emitting diode on which a pixel array is disposed (Fig. 1 and para. 31), each pixel in the pixel array comprising a micro-light emitting diode chip (inherently included in any LED, Fig. 1 and para. 31) , wherein the first interface circuit is implemented with a bidirectional serial interface having a feedback loop type between adjacent timing controllers (Figs. 1 and 3 and paras. 35 and 38), and wherein the set board is connected to a first timing controller in a first display module through a second interface circuit (Figs. 1, 3 and 4 and paras. 32, 45 and 46) and provides the control command signal to the first timing controller (Figs. 1, 3 and 4 and paras. 32, 45 and 46), wherein the set board transfers image data to the plurality of timing controllers through an interface circuit implemented based on a V-by-One scheme (Fig. 1 and para. 36).
Yang does not show that the image data interface is separate from the command signal interface.
Jeong shows that an image data interface is separate from a command (control) signal interface (Fig. 11 and para. 97).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the teachings of Yang with those of Jeong because designing the system in this way allows the device to reduce energy consumption (via BLE, for example, para. 97).
As to claim 2, Yang shows that the timing controller comprises a mode (i.e. bypass) selector (Fig. 3 and para. 45), and the set board is further configured to control the mode selector to activate a bypass communication mode (Fig. 3 and para. 45).
As to claim 3, Yang shows that the control command signal is transferred to a target timing controller on the basis of a bypass scheme through a serial interface in a first direction to cause the target timing controller to execute the target operation (Figs. 3 and 4 and paras. 45 and 46), where in the bypass scheme, the control command signal passes through a timing controller previous to the target timing controller in a signal transferring direction, the first direction indicating a direction from the set board to the display module (Figs. 3 and 4 and paras. 45 and 46).
As to claim 4, Yang shows that the target timing controller generates a control response signal corresponding to the control command signal (Figs. 3 and 4 and paras. 45 and 46), and feedbacks the control response signal to the first timing controller serving as the target timing controller, on the basis of the bypass scheme through a serial interface in a second direction opposite to the first direction (Figs. 3 and 4 and paras. 45 and 46).
As to claim 5, Yang shows that the control command signal comprises: a header region including a command signal representing a kind of a control command and position information about a display module corresponding to the target timing controller (inherently the case, Fig. 7 and paras. 52 and 56); a data region including control command data; and an information region including a check flag signal for transmission/reception error check (Fig. 7 and para. 52).
As to claim 6, Yang shows that the control command signal passes through a certain timing controller previous to the target timing controller in the first direction (para. 38), the timing controller analyzes only the header region while transferring the control command signal to a subsequent timing controller in the first direction (para. 56).
As to claim 16, Yang shows that wherein the tiling display apparatus operates in a bypass communication mode (Fig. 3 and para. 45), and in one bypass communication, one of the plurality of timing controllers is taken as the target timing controller (Figs. 3, 4 and 7 and paras. 45, 46, 52 and 56).
As to claim 20, Yang shows that the first interface circuit includes a first transmission cable (i.e. first interface between source controller and first serial unit, Figs. 1, 3 and 4 and paras. 32, 45 and 46), and the image data interface circuit includes a separate transmission cable physically separated from the first transmission cable (i.e. any other feed forward interface, Figs. 1, 3 and 4 and paras. 32, 45 and 46).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang and Jeong as combined above in view of Kim et al. (US Pub. No. 2018/0165051 A1).
As to claim 17, Yang shows that the second interface circuit is implemented with a unidirectional serial interface or the bidirectional serial interface (para. 38).
Yang does not show that the bidirectional serial interface is implemented as a dual serial peripheral interface (SPI), and the unidirectional serial interface is implemented as a single SPI.
Kim shows that a bidirectional serial interface is implemented as a dual serial peripheral interface (SPI) (i.e. HDMI), and a unidirectional serial interface is implemented as a single (i.e. HDMI, Fig. 4 and paras. 74 – 92).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the teachings of Yang with those of Kim because designing the system in this way allows the device to perform error detection (para. 80).
Allowable Subject Matter
Claims 7 – 15, 18 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites that “… the control response signal comprises: a header region including position information about the first timing controller and information representing whether the command signal is normal; a data region including control execution data; and an information region including a check flag signal for transmission/reception error check.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 8 contains allowable subject matter at least by virtue of its dependence on claim 7.
Claim 9 recites that “…that the tiling display apparatus operates in an asynchronous overlap communication mode, each of the plurality of timing controllers is the target timing controller, and wherein each timing controller analyzes the header region and stores the control command data in a target memory while transferring the control command signal to a subsequent timing controller in the first direction.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 10 contains allowable subject matter at least by virtue of its dependence on claim 9.
Claim 11 recites that “…the tiling display apparatus operates in the synchronous overlap communication mode, each of the plurality of timing controllers is the target timing controller, and wherein each timing controller analyzes the header region and stores the control command data in a temporary buffer while transferring the control command signal to a subsequent timing controller in the first direction.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claims 12 – 15 contain allowable subject matter at least by virtue of their dependence on claim 11.
Claim 18 recites that “…the timing controller further comprises a multiplexer, a controller, and a temporary buffer that is activated in the synchronous overlap communication mode and is deactivated in the other communication modes.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
Claim 19 recites that “…the micro-light emitting diode chip is transferred from R/G/B donors and is mounted on a thin film transistor backplane.”
The prior art does not show this configuration; therefore, this claim contains allowable subject matter.
CONCLUSION
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/CARL ADAMS/Examiner, Art Unit 2627
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