DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1, line 8 recites “a received detection signal”, which should be -- the received detection signal– because this term was previously presented in the claim; : Claim 1, line 10 recites “the received signal”, which should be -- the received detection signal– because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 5 is objected to because of the following informalities: Claim 5, line 12 recites “a detection signal”, which should be -- a second detection signal – in order to distinguish this second detection signal (Figure 1, part VZC) from the different detection signal (Figure 1, part VDET); Claim 5, line 15 recites “a signal level of a received signal”, which should be -- the signal level of the second detection signal – because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fogg (US 2016/0172999), in view of Hasegawa (US 2008/0224674).
Regarding claim 1, claim 5 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 2, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 3, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 4, claim 8 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 5, Fogg discloses (see figures 1-11) a switching regulator (figure 7, part 700), comprising: an error amplification circuit (figure 7, part 722), amplifying a difference between a first reference voltage (figure 7, part VREF3) and a feedback voltage (figure 7, part VFB) proportional to an output voltage (figure 7, part VO) and outputting an error voltage (figure 7, part output of 722); a comparator (figure 7, part CMP1), comparing a voltage (figure 7, part lower input voltage of CMP1) with a second reference voltage (figure 7, part VREF1) and outputting a detection signal (figure 7, part OV) comprising a signal level (figure 7, part OV; high/low signal level) corresponding to a comparison result (figure 7, part CMP1); a high-side transistor (figure 7, part M); a low-side transistor (figure 7, part R), connected in series with the high-side transistor (figure 7, part M); an inductor (figure 7, part L), comprising a first end (figure 7, part L; left end) connected to a connection point (figure 7, part connection point between M and R) between the high-side transistor (figure 7, part M) and the low-side transistor (figure 7, part R), and a second end (figure 7, part L; right end) connected to an output terminal (figure 7, part terminal at VO); a detection circuit (figure 7, part detection circuit generated by CMP2 and 734), containing an input port (figure 7, part input port at VSEN at upper input terminal of CMP2) connected to the connection point (figure 7, part connection point between M and R), and an output port (figure 7, part output port at SC from 734) which detects (figure 7, part detection circuit generated by CMP2 and 734; through VSEN) a current flowing from the second end to the first end of the inductor (figure 7, part current from the right end to the left end of L [reverse]), and outputs a detection signal (figure 7, part SC) comprising a signal level (figure 7, part SC; high/low signal level) corresponding to a detection result of the current (figure 7, part detection circuit generated by CMP2 and 734); and a control circuit (figure 7, part control circuit generated by 723-726), controlling the high-side transistor (figure 7, part M; off; through 726) and the low-side transistor to be off (figure 7, part R; off; through 725) in response to a signal level of a received signal (figure 7, part SC; low level) indicating that the voltage (figure 7, part lower input voltage of CMP1) and the second reference voltage (figure 7, part VREF1) based on the detection signal (figure 7, part OV) and that the current (figure 7, part current through L) is detected (figure 7, part through VSEN and CMP2) based on the detection signal (figure 7, part SC) (paragraphs [0042]-[0043] and [0061]-[0062]; The over voltage detection circuit CMP1 has a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal is electrically coupled to the feedback circuit 204 to receive the feedback signal VFB, and the inverting input terminal is configured to receive an over voltage threshold VREF1. The comparator CMP1 compares the over voltage threshold VREF1 with the feedback signal VFB and generates an over voltage detection signal OV at the output terminal. The over current detection circuit CMP2 has a non-inverting input terminal, an inverting input terminal, an output terminal and an enable terminal. The non-inverting input terminal is electrically coupled to the switching node to receive a current sense signal VSEN which is a voltage drop across the rectifier R in the embodiment illustrated in FIG. 2, the inverting input terminal is configured to receive an over current threshold VREF2, and the enable terminal is electrically coupled to the output terminal of the over voltage detection circuit CMP1 to receive the over voltage detection signal OV. When the over current detection circuit CMP2 is enabled by the over voltage detection signal OV, it compares the current sense signal VSEN with the over current threshold VREF2 and generates an over current detection signal OC at the output terminal. The timing circuit 231 has a first input terminal and an output terminal… he cycle counting circuit 734 is electrically coupled to the output terminal of the over current detection circuit CMP2 to receive the over current detection signal OC, and the cycle counting circuit 734 generates a cycle counting signal SC based on the over current detection signal OC… The cycle counting circuit 734 starts counting cycles when the over current detection signal OC goes to high, and outputs a low level cycle counting signal SC when the cycles reaches a predetermined number. Such low level cycle counting signal SC overrides any value applied to the second input terminal of the AND gate 726 and to the first input terminal and the second input terminal of the AND gate 723, thus both the first control signal HS and the second control signal LS become logic low. Accordingly, both the main switch M and the rectifier R are turned off and the switching circuit 701 stops switching actions. In this way, the over-charge of the input voltage is prevented).
Fogg does not expressly disclose comparing the error voltage with a second reference voltage and outputting a detection signal comprising a signal level corresponding to a comparison result; indicating that the error voltage falls below the second reference voltage based on the detection signal.
Hasegawa teaches (see figures 1-9) an error amplification circuit (figure 4, part ERA1), amplifying a difference (figure 4, part ERA1) between a first reference voltage (figure 4, part e1) and a feedback voltage (figure 4, part feedback from R1/R2) proportional to an output voltage (figure 4, part Vout) and outputting an error voltage (figure 4, part Veo); a comparator (figure 4, part COMP2), comparing the error voltage (figure 4, part Veo) with a second reference voltage (figure 4, part Vth) and outputting a detection signal (figure 4, part CTL) comprising a signal level (figure 4, part CTL; high/low signal level) corresponding to a comparison result (figure 4, part COMP2); indicating (figure 4, part COMP2) that the error voltage (figure 4, part Veo) falls below the second reference voltage (figure 4, part Vth) based on the detection signal (figure 4, part CTL) (paragraphs [0038] and [0049]; a voltage comparator COMP2 and a selector circuit SE. An output voltage Veo is input to the inverted input terminal of the voltage comparator COMP2, and a reference voltage Vth is input to the non-inverted input terminal of the voltage comparator COMP2. A control signal CTL is output from the voltage comparator COMP2… The lighter the load becomes, the higher the output voltage Vout rises, and the lower the output voltage Veo falls. If the output voltage Veo falls below the reference voltage Vth, the voltage comparator COMP2 determines that a low load state exists, and the control signal CTL transitions from a low level to a high level).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the comparator of Fogg with the comparator features as taught by Hasegawa (more specific, modify the way is detected the operation mode of the regulator) and obtain a switching regulator, comprising: an error amplification circuit, amplifying a difference between a first reference voltage and a feedback voltage proportional to an output voltage and outputting an error voltage; a comparator, comparing the error voltage with a second reference voltage and outputting a detection signal comprising a signal level corresponding to a comparison result; a high-side transistor; a low-side transistor, connected in series with the high-side transistor; an inductor, comprising a first end connected to a connection point between the high-side transistor and the low-side transistor, and a second end connected to an output terminal; a detection circuit, containing an input port connected to the connection point, and an output port which detects a current flowing from the second end to the first end of the inductor, and outputs a detection signal comprising a signal level corresponding to a detection result of the current; and a control circuit, controlling the high-side transistor and the low-side transistor to be off in response to a signal level of a received signal indicating that the error voltage falls below the second reference voltage based on the detection signal and that the current is detected based on the detection signal, because it provides more accurate and efficient operation detection in order to improve power conversion efficiency (Abstract).
Regarding claim 6, Fogg and Hasegawa teach everything claimed as applied above (see claim 5). Further, Fogg discloses (see figures 1-11) the detection circuit (figure 7, part detection circuit generated by CMP2 and 734) is configured to determine that the current (figure 7, part current through L) is detected (figure 7, part through VSEN at CMP2) in a case where a voltage (figure 7, part VSEN) at the connection point (figure 7, part connection point between M and R) between the high-side transistor (figure 7, part M) and the low-side transistor (figure 7, part R) is higher than OV (figure 7, part through VREF2 at CMP2).
Regarding claim 7, Fogg and Hasegawa teach everything claimed as applied above (see claim 5). Further, Fogg discloses (see figures 1-11) the second reference voltage (figure 7, part VREF1) is a predetermined voltage (figure 7, part VREF1). However, Fogg does not expressly disclose which is lower than the error voltage in response to an average value of an inductor current being OA.
Hasegawa teaches (see figures 1-9) the second reference voltage (figure 4, part Vth) is a predetermined voltage (figure 4, part Vth) which is lower than the error voltage (figure 4, part Veo) in response to an average value of an inductor current being OA (figure 4, part average value IL being 0A at normal operation [not light load]; in order to detect the light load state, the predetermined voltage Vth is settled to be lower than error voltage Veo to detect when Veo falls below Vth that is a representation of light load state) (paragraph [0049]; The lighter the load becomes, the higher the output voltage Vout rises, and the lower the output voltage Veo falls. If the output voltage Veo falls below the reference voltage Vth, the voltage comparator COMP2 determines that a low load state exists, and the control signal CTL transitions from a low level to a high level).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the comparator of Fogg with the comparator features as taught by Hasegawa (more specific, modify the way is detected the operation mode of the regulator) and obtain the second reference voltage is a predetermined voltage which is lower than the error voltage in response to an average value of an inductor current being OA, because it provides more accurate and efficient operation detection in order to improve power conversion efficiency (Abstract).
Regarding claim 8, claim 7 has the same limitations, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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