DETAILED ACTION
1. This office action is in response to the Application No. 19060794 filed on 05/14/2026. Claims 1-18 are presented for examination and are currently pending. Applicant’s arguments have been carefully and respectfully considered.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on
05/14/2026 has been entered.
Response to Arguments
4. The Applicant’s argument on pages 11-12 that “the amended claims here improve how the neural network system itself operates by (a) replacing static, offline pruning with a multi-level supervisory architecture that performs pruning during operation of the network; (b) using adaptive thresholds that respond to network state, rather than fixed predetermined thresholds, to detect sparsity; and (c) coordinating pruning decisions across a structural hierarchy of supervisory nodes by exchanging resource and sparsity information across levels. These are improvement to system architecture and runtime behavior”.
Furthermore, on page 10-11, the Applicant argued that “The specification expressly describes the architectural improvements as occurring during operation of the neural network: "This sophisticated pruning mechanism allows for real-time optimization of the neural network structure through controlled architectural modifications while maintaining operational stability through support pathways and continuous performance validation." Spec. [[0007]. "These structural modifications execute dynamically during inference operations, enabling machine learning core 1240 to implement real-time adaptation to evolving data distributions and processing requirements." Spec. [0252]”.
The above arguments are persuasive because it improves the functioning of the technological field of the operation of the neural network. As a result, the 101 rejection has been withdrawn.
The Applicants argument regarding the prior art has been considered and the Examiner is withdrawing the rejections in the previous Office action because Applicant’s amendment necessitated new grounds of rejection presented in this Office Action. It is noted that arguments regarding independent claims 1 and 10 have been considered but are moot because new references have now been used to remap the independent claims 1 and 10.
Furthermore, Abraham which was applied in the previous Office Action is still relevant to the instant dependent claims. As a result, their teachings have been used in this Office Action. The dependent claims 2-9 and 11-18 which depend directly or indirectly from independent claims 1 and 10 are not patentable because the instant claims are still obvious over the prior art of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-4, 6-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. ("Cambricon-S: Addressing irregularity in sparse neural networks through a cooperative software/hardware approach." 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018) in view of Ghosh et al. ("Energy-efficient approximate edge inference systems." ACM Transactions on Embedded Computing Systems 22.4 (2023): 1-50) and further in view of Nurvitadhi et al. (US11636327 published 04/25/2023)
Regarding claim 1, Zhou teaches a computer system comprising a hardware memory (The accelerator has 53KB SRAM in total (pg. 23, section A. Hardware Characteristics); We further design a hardware accelerator (abstract); Note that we assume all the accelerators are plugged to a main memory model allowing a bandwidth up to 256 GB/s (pg. 23, section: Hardware Accelerators); Our accelerator achieves nearly the ideal speedup by hiding the DMA memory access behind the computation with the help of ping-pong buffering, pg. 25, second para., section: Sparsity Sensitivity. The Examiner notes an accelerator is a deep learning processor),
wherein the computer system is configured to execute software instructions (Here we define a VLIW-style instruction set for the accelerator, pg. 21, first para.)
operate a neural network comprising interconnected nodes arranged in layers (Here we analyze the coarse-grained pruned network for accelerator design principles, using a fully-connected layer as a driving example (see Figure 10)(pg. 20, Section IV. Design Principles); Regarding the example in Figure 10, the actual operations regarding to static sparsity are 12 multiplications, 9 additions with 16 input data, or 6 multiplications, 3 additions with 8 input data when considering additional dynamic sparsity, pg. 20, right col., second para.);
implement a hierarchical supervisory system (Accelerator Architecture, Fig. 11) monitoring the neural network during operation of the neural network (Thus, during sparse neural networks processing, accelerator needs to select neurons/synapses based on neuron values (dynamic sparsity) and synapse indexes (static sparsity), pg. 21, third para.) through multiple supervisory levels (NSM, NFU and CP, Fig. 11) comprising low-level supervisory nodes (neuron selector module (NSM) in Fig. 11 comprising target string and indexing string in Fig. 12) monitoring subsets of operational neurons of the neural network (The NSM receives input neurons from the NBin and synapse indexes from the SIB, then produces the filtered neurons (static sparsity) and the indexing string that are broadcast to all the PEs in NFU (pg. 21, left col., second para., Fig. 11); The NSM module processes the static sparsity by selecting the needed input neurons, see Figure 12 ... Note that, the selected neurons and indexing strings are shared by multiple output neurons (pg. 21, right col., first para.); For the example in Figure 10 to select from 8 neurons with zero-valued n4, n6, n8, NSM produce the final target string to find the needed neurons n 1, n7 and generate indexing string for later synapses selection, pg. 21, left col., last para.),
mid-level supervisory nodes (neural functional unit (NFU) comprising processing elements (PEs), Fig. 11) coordinating across the low-level supervisory nodes (Note that, the selected neurons and indexing strings are shared by multiple output neurons, thus broadcast to the PEs in NFU (pg. 21, right col., first para., Fig. 11); We design a neural functional unit (NFU) that has multiple processing elements (PEs) to compute different output neurons in parallel. Each PE contains a local synapse selector module (SSM) to process the dynamic sparsity, pg. 20, right col., last para.), and
high-level supervisory nodes (control processor (CP) and an instruction buffer (IB), Fig. 11) coordinating across the mid-level supervisory nodes (The CP is the root of our accelerator and controls the whole execution process. It decodes the instructions from the inner IB efficiently for execution coordination, memory accesses and data organization. The CP monitors the state of every module by setting the corresponding control registers (pg. 22, right col., Section C. Control); The CP decodes various instructions from IB efficiently into detailed control signals for all other modules, pg. 21, left col., first para.),
wherein the hierarchical supervisory system (Accelerator Architecture, Fig. 11) collects activation data (Each PE loads the compressed synapses from its local SB as synapses are independent among different output neurons and hence can be stored separately in PEs, pg. 21, right col., second para. The Examiner notes that instant specification discloses “activation data refers to information about the activity of neurons in a neural network” (instant specification: US20250363363 [0083])),
identifies operation patterns (the dense layer has 24 multiplications, 21 additions with 32 input data, which has 2.14×/5.00× more operations and 2×/4× more data than static sparsity/static+dynamic sparsity, respectively, pg. 20, right col., second para.),
implements architectural changes during operation of the neural network (Regarding the example in Figure 10, the actual operations regarding to static sparsity (pg. 20, right col., second para.); For static sparsity, synapses (Figure 2 (b)) and neurons (Figure 2 (c)) are permanently removed from the network, pg. 16, right col., third para.),
and manages resource redistribution (The key feature of the accelerator is the Indexing Module (IM), which selects and transfers the needed neurons to connected PEs thus focusing on synapse sparsity only; but it takes up to 31.07% of the total area and 34.83% of the energy cost (pg. 17, right col. second para.); It decodes the instructions from the inner IB efficiently for execution coordination, memory accesses and data organization, pg. 22, Section C. Control);
implement a meta-supervisory system (input buffer (NBin), an output buffer (NBout), a synapse index buffer (SIB) and Tm synapse buffers (SBs), as shown in Fig. 11, pg. 22. left col., second para.) that tracks supervisory behavior patterns (As the data processed in our accelerator have different behaviors, we split storage into four parts: an input buffer (NBin), an output buffer (NBout), a synapse index buffer (SIB) and Tm synapse buffers (SBs), as shown in Figure 11. In order to leverage the overlap between computation and DMA memory access, we implement the buffers in a ping-pong manner, pg. 22, Section B. Storage),
stores successful modification and pruning patterns (In order to retain the small size of indexes after coarse-grained pruning, we employ a high efficient indexing method. Particularly, we store the synaptic weights in a compact way. Only the existing synapses (non-pruned) are stored together with their corresponding indexes that indicate the connections between input and output neurons (“synapse indexes” in Figure 10). We store the neurons as they were stored in dense networks, i.e., “0” will be used as neuron value and stored if a neuron does not exist due to pruning or ReLU activation function, pg. 21, left col., third para.), and
extracts generalizable principles (In this paper, we propose a generalized coarse-grained pruning technique which can exploit local convergence in neural networks and reduce the irregularity drastically (20.13 × on average) (pg. 26, right col., second para.); For generality, we store synaptic weights compactly regarding static sparsity. As shown in Figure 10, for each output neuron, the first and the fourth synapses (STi1,STi4) are the two needed synapses for computation, pg. 21, right col., second to the last para.); and
Zhou does not explicitly teach wherein the computer system is configured to execute software instructions stored on nontransitory machine- readable storage media that: detects network sparsity using thresholds that adapt based on neural network state, coordinates pruning decisions across the multiple supervisory levels by exchanging information about resource availability and network sparsity, manage signal transmission pathways providing direct connections between non-adjacent layers of the neural network with signal modification and temporal coordination during transmission.
Ghosh teaches detects network sparsity using thresholds that adapt based on neural network state (we designed a new quality-driven iterative pruning scheduler for QUSP that automatically calculates the pruning duration d, and the initial sparsity value ss and the final sparsity value sf for each layer l and for each quality bound qi ∈ Qb. These sparsity values are generated using a quality-driven sparsity selector, as described in Algorithm 1. This process uses Γ to find the maximum tolerable sparsity of each DNN layer per qi. The thresholds used in this algorithm were empirically determined, pg. 77:21, first para.),
coordinates pruning decisions across the multiple supervisory levels by exchanging information about resource availability (Quality-Driven Structured Pruning (QUSP) methodology ... memory approximation using DRAM refresh rate reduction and significance-driven allocation of DNN weights and feature maps in different DRAM quality bins, pg. 77:3, first para.) and network sparsity (Essentially, pruning introduces sparsity in entire filters depending on their importance, and thinning permanently eliminates these sparse filters and dependent OFMs, thereby reducing computational complexity (FLOPs) and decreasing the energy consumption of the compute sub system, pg. 77:20, first para.),
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Zhou to incorporate the teachings of Ghosh for the benefit of structured pruning and thinning to facilitate energy-efficient inference on resource-constrained edge devices due to their simplicity (Ghosh, pg. 77:19, second para.)
Zhou and Ghosh does not explicitly teach wherein the computer system is configured to execute software instructions stored on nontransitory machine- readable storage media that: manage signal transmission pathways providing direct connections between non-adjacent layers of the neural network with signal modification and temporal coordination during transmission.
Nurvitadhi teaches wherein the computer system is configured to execute software instructions stored on nontransitory machine- readable storage media that (In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions which, when executed, perform operations for system and user software, col. 4, lines 41-44):
manage signal transmission pathways providing direct connections between non-adjacent layers of the neural network (wherein the hardware accelerator supports arbitrary connections across non-adjacent layers of the arbitrary irregular neural network, see claim 11) with signal modification and temporal coordination during transmission (If a temporal computation is utilized, unimportant (e.g., zero values) of input vectors can be skipped to improve efficiency and reduce computation time (col. 43, lines 16-19); a skip circuitry to track unimportant input operands to be skipped by the scheduler (col. 76, lines 56-57); At operation 3240, the scheduler of the sparsity management unit receives the vector 3230 and skips the unimportant values (e.g., zero values for the 2nd and 4th bits of vector 3230), col. 43, lines 50-53)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Zhou and Ghosh to incorporate the teachings of Nurvitadhi for the benefit of a neural networks wherein reduced computations for sparsity (has zeros, or generally, unimportant values) is supported in addition to improve efficiency from reducing compute, storage, and data moves while maintaining still good accuracy (Nurvitadhi, col. 41, lines 41-44)
Regarding claim 2, Modified Zhou teaches the computer system of claim 1, Ghosh teaches wherein the hierarchical supervisory system detects network sparsity using thresholds that adapt based on neural network state (we designed a new quality-driven iterative pruning scheduler for QUSP that automatically calculates the pruning duration d, and the initial sparsity value ss and the final sparsity value sf for each layer l and for each quality bound qi ∈ Qb. These sparsity values are generated using a quality-driven sparsity selector, as described in Algorithm 1. This process uses Γ to find the maximum tolerable sparsity of each DNN layer per qi. The thresholds used in this algorithm were empirically determined, pg. 77:21, first para.).
The same motivation to combine independent claim 1 applies here.
Regarding claim 3, Modified Zhou teaches the computer system of claim 1, Ghosh teaches wherein the hierarchical supervisory system exchanges information about resource availability (Quality-Driven Structured Pruning (QUSP) methodology ... memory approximation using DRAM refresh rate reduction and significance-driven allocation of DNN weights and feature maps in different DRAM quality bins, pg. 77:3, first para.) and network sparsity (Essentially, pruning introduces sparsity in entire filters depending on their importance, and thinning permanently eliminates these sparse filters and dependent OFMs, thereby reducing computational complexity (FLOPs) and decreasing the energy consumption of the compute sub system, pg. 77:20, first para.) across the multiple supervisory levels (This article introduces the concept of an approximate edge inference system (AxIS) and proposes a systematic methodology to perform joint approximations between different subsystems in a deep neural network (DNN)-based edge inference system, abstract)
The same motivation to combine independent claim 1 applies here.
Regarding claim 4, Modified Zhou teaches the computer system of claim 1, Ghosh teaches wherein the meta-supervisory system maintains network stability while identifying patterns across implemented pruning decisions (The algorithm increments αi of each subsystem (i ∈ s) individually and performs a Q-E SA to measure quality Qαi+1 i and energy Eαi+1 i at each configuration of the system. The algorithm identifies all subsystems whose approximations do not meet the quality bound QB. Furthermore, it eliminates them from all subsequent SA rounds and thus drastically reduces/prunes the design search space pg. 77:31, last para.).
The same motivation to combine independent claim 1 applies here.
Regarding claim 6, Modified Zhou teaches the computer system of claim 1, Ghosh teaches wherein the signal transmission pathways modify signal strengths based on observed transmission effectiveness and detected network sparsity (we designed a new quality-driven iterative pruning scheduler for QUSP that automatically calculates the pruning duration d, and the initial sparsity value ss and the final sparsity value sf for each layer l and for each quality bound qi ∈ Qb. These sparsity values are generated using a quality-driven sparsity selector, as described in Algorithm 1. This process uses Γ to find the maximum tolerable sparsity of each DNN layer per qi ... This iterative process is followed by network thinning that considers data dependencies across layers and then physically removes the pruned filters from the CONVlayers, along with bias and the relevant coefficients of the batch normalization layers following that CONV layer. ... On top of that, the weight filters corresponding to these pruned OFMs are also removed. These cumulative efforts result in a substantial reduction in the number of FLOPs and weights, which speeds up the inference and reduces the energy of the computation subsystem., pg. 77:21, first para. The Examiner notes that the removal of the pruned filters and OFMs are the pathways that are modified).
The same motivation to combine independent claim 1 applies here.
Regarding claim 7, Modified Zhou teaches the computer system of claim 1, Zhou teaches wherein the meta-supervisory system associates context identifiers with the stored modification and pruning patterns (we explain clearly how we store and index the sparse data in accelerator. In order to retain the small size of indexes after coarse-grained pruning, we employ a high efficient indexing method. Particularly, we store the synaptic weights in a compact way. Only the existing synapses (non-pruned) are stored together with their corresponding indexes that indicate the connections between input and output neurons (“synapse indexes” in Figure 10). We store the neurons as they were stored in dense networks, i.e., “0” will be used as neuron value and stored if a neuron does not exist due to pruning or ReLU activation function, pg. 21, left col., third para.).
Regarding claim 8, Modified Zhou teaches the computer system of claim 1, Zhou teaches wherein the hierarchical supervisory system (Accelerator Architecture, Fig. 11) validates neural network performance during implementation of the architectural changes (Regarding sparse representation, our accelerator achieves 331.1× and 19.3× speedup over CPU-Sparse and GPU-cuSparse, respectively. Compared against the state-of-the-art accelerators DianNao and Cambricon-X, our accelerator achieves 13.10 × and 1.71 × speedup, which shows the high performance of our accelerator, pg. 23, right col., last para.).
Regarding claim 9, Modified Zhou computer system of claim 1, Ghosh teaches wherein the meta-supervisory system adapts future pruning decisions based on outcomes of previous architectural changes (The pruning schedule is another critical component of any pruning algorithm. This determines the number of iterations to run (duration), the pruning criteria, the number of filters to prune per iteration, and the frequency of pruning ... At each iteration, QUSP evaluates the importance of the filters based on the selected saliency metric and prunes K less significant filters based on the sparsity percentage inferred from the schedule st. After d iterations, we clone the current pruned model to M1 for the first quality bound q1 and continue pruning until B models are created, one for each qi, pg. 77:21, first and second para.).
The same motivation to combine independent claim 1 applies here.
Regarding claim 10, claim 10 is similar to claim 1. It is rejected in the same manner and reasoning applying.
Regarding claim 11, claim 11 is similar to claim 2. It is rejected in the same manner and reasoning applying.
Regarding claim 12, claim 12 is similar to claim 3. It is rejected in the same manner and reasoning applying.
Regarding claim 13, claim 13 is similar to claim 4. It is rejected in the same manner and reasoning applying.
Regarding claim 15, claim 15 is similar to claim 6. It is rejected in the same manner and reasoning applying.
Regarding claim 16, claim 16 is similar to claim 7. It is rejected in the same manner and reasoning applying.
Regarding claim 17, claim 17 is similar to claim 8. It is rejected in the same manner and reasoning applying.
Regarding claim 18, claim 18 is similar to claim 9. It is rejected in the same manner and reasoning applying.
6. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. ("Cambricon-S: Addressing irregularity in sparse neural networks through a cooperative software/hardware approach." 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018) in view of Ghosh et al. ("Energy-efficient approximate edge inference systems." ACM Transactions on Embedded Computing Systems 22.4 (2023): 1-50) in view of Nurvitadhi et al. (US11636327 published 04/25/2023) and further in view of Abraham et al. ("Back to the Future: Reversible Runtime Neural Network Pruning for Safe Autonomous Systems." 2024 Design, Automation & Test in Europe Conference & Exhibition (25 March 2024). IEEE, 2024).
Regarding claim 5, Modified Zhou teaches the computer system of claim 1, they do not explicitly teach wherein the hierarchical supervisory system establishes support pathways to enable reversal of architectural changes during pruning.
Abraham teaches wherein the hierarchical supervisory system establishes support pathways to enable reversal of architectural changes during pruning (Our approach allows the pruned model to quickly revert to the full model when unsafe behavior is detected, pg. 6, right col, first para.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Modified Zhou to incorporate the teachings of Abraham for the benefit of enhancing safety and reliability, and providing seamless reversion to the accurate version of the model, demonstrating its applicability for safe autonomous systems design (Abraham, abstract)
Regarding claim 14, claim 14 is similar to claim 5. It is rejected in the same manner and reasoning applying.
Conclusion
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/M.G./Examiner, Art Unit 2148
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