DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The new title has been accepted.
Response to Amendment
Applicant’s arguments filed 07/21/2026 have been fully considered.
Necessary amendments have been made to overcome the existing 35 U.S.C. 112(b) rejections; the rejections have been withdrawn.
In regards to the arguments pertaining to 35 U.S.C. 103 rejections, the arguments are not persuasive. The Applicant argues that neither Nemati nor Chang teach "acquiring first information indicating a state of a defect of a member in a semiconductor device; generating third information including a physical location of a failure and a type of the failure in the semiconductor device.”
However, the Examiner respectfully disagrees.
Nemati teaches acquiring first information indicating a state of a defect of a member in a semiconductor device (Nemati, [0071] tracking and logging correctable and uncorrectable error)
Furthermore, Chang teaches generating third information including a physical location of a failure and a type of the failure in the semiconductor device (Chang, [0041] "If any flag about the channel data deterioration is asserted, the controller 106 queries the FIFO buffer Read_FIFO according to the channel number CH # corresponding to the flagged channel, and thereby obtains physical addresses PBAs recorded in the FIFO buffer Read_FIFO and corresponding to the channel number CH #. The controller 106 may record the obtained physical addresses PBAs in the random access memory in a deterioration data structure. The physical addresses PBAs recorded in the deterioration data structure 118 are regarded as physical addresses candidates to be checked. According to the physical addresses candidates presented in the deterioration record data structure 118, the controller 116 reads the flash memory 104 to determine which physical address candidate really happens the deterioration." This teaches acquiring the physical location of the failure and verifying the error at the location)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nemati et al (US 20230305924 A1) in view of Chang et al (US 20230266912 A1).
Per claim 1, Nemati teaches
An evaluation method comprising:
acquiring first information indicating a state of a defect of a member in a semiconductor device ([0071] “track and log correctable and uncorrectable errors” Tracking requires the acquisition of the said information);
… prestored second information, wherein the prestored second information indicates that the location of the failure and the type of the failure are associated with the first information (FIG. 7 Example UE Logger Data Structure 610; [0072] “UE logger 610, in the illustrated embodiment, is configured to log detected memory errors and track certain information (e.g., physical address, error source, client identifier, etc., as discussed in detail below). In the illustrated embodiment, UE logger 610 is specifically configured to log detected uncorrectable memory errors. In some embodiments, UE logger 610 tracks the sources of uncorrectable errors.”)
controlling whether fourth information for specifying the type of the failure of the semiconductor device is returned to a control device for controlling the semiconductor device, based on an access request from the control device and the third information; and ([0039] “read to the location in turn causes a UE” when a control device tries to access the location in which the corruption has been detected, the uncorrectable error is produced. It is the Examiner’s interpretation that because a distinction is made between uncorrectable error (UE) and a correctable error (CE), the assertion of the uncorrectable error teaches “the type of the failure” in the claim language. Furthermore, since the information is only returned to the control device with the request access, it teaches the “controlling…” clause of the claim limitation)
evaluating an operation of the control device after the fourth information is returned ([0029] “Memory control circuit 101, in the illustrated embodiment, receives access requests 109 via multiple virtual channels 110.” Any further read/write request from the control device will be received and will be evaluated through the same process)
Nemati fails to teach
generating third information including a physical location of a failure and a type of the failure in the semiconductor device based on the first information and prestored second information
Chang teaches
generating third information including a location of a failure and a type of the failure in the semiconductor device based on the first information and prestored second information (Chang, [0041] "If any flag about the channel data deterioration is asserted, the controller 106 queries the FIFO buffer Read_FIFO according to the channel number CH # corresponding to the flagged channel, and thereby obtains physical addresses PBAs recorded in the FIFO buffer Read_FIFO and corresponding to the channel number CH #. The controller 106 may record the obtained physical addresses PBAs in the random access memory in a deterioration data structure. The physical addresses PBAs recorded in the deterioration data structure 118 are regarded as physical addresses candidates to be checked. According to the physical addresses candidates presented in the deterioration record data structure 118, the controller 116 reads the flash memory 104 to determine which physical address candidate really happens the deterioration." This teaches acquiring the physical location of the failure and verifying the error at the location)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Nemati with the teaching of Chang in order to teach the use of referring to the table with the error details in order to determine the type of error and the error location because, as stated in Nemati, it is a conventional method in doing so ([0055]).
Per claim 2, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein the second information further indicates a correspondence relationship between a member to be a target of the defect, a state of the defect, the type of the failure, and the location of the failure of the semiconductor device. (Nemati, [0077] “FIG. 7 is a diagram illustrating an example UE logger data structure configured to log uncorrectable memory errors, according to some embodiments. In the illustrated embodiment, example UE logger data structure 610 includes valid, physical address, client identifier, and error source fields.” [0080] “the client identifier field identifies the client circuitry in a SoC that previously accessed the data”)
Per claim 3, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein the third information includes a physical address indicating the location of the failure of the semiconductor device and the type of the failure. (Most of the claim limitation language has been taught in claim 1, and the only additional claim limitation to be considered is “physical address indicating the location of the failure.” Since the information of physical address is available (Nemati, FIG. 7 which represents the prestored second information) and since this information is being used to determine whether the information is getting accessed by a specific controller (claim 1), generating not only any address (claim 1) but a physical address would yield a predictable result and would therefore make sense to combine)
Per claim 4, Nemati in view of Chang teaches
The evaluation method according to claim 3,
wherein when the third information includes the physical address of the semiconductor device included in the access request from the control device, the fourth information is returned to the control device. (Nemati, [0039] “read to the location in turn causes a UE”)
Per claim 5, Nemati in view of Chang teaches
The evaluation method according to claim 3, further comprising:
generating the third information by referring to information configured to specify the physical address, in addition to based on the first information and the second information. (Chang, [0041] "If any flag about the channel data deterioration is asserted, the controller 106 queries the FIFO buffer Read_FIFO according to the channel number CH # corresponding to the flagged channel, and thereby obtains physical addresses PBAs recorded in the FIFO buffer Read_FIFO and corresponding to the channel number CH #. The controller 106 may record the obtained physical addresses PBAs in the random access memory in a deterioration data structure. The physical addresses PBAs recorded in the deterioration data structure 118 are regarded as physical addresses candidates to be checked. According to the physical addresses candidates presented in the deterioration record data structure 118, the controller 116 reads the flash memory 104 to determine which physical address candidate really happens the deterioration." This teaches acquiring the physical location of the failure and verifying the error at the location)
Per claim 6, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein the first information includes a state of the defect occurring in a specific member disposed at a specific location of the semiconductor device. (Nemati, ([0071] “track and log correctable and uncorrectable errors,” FIG. 7 physical address, client identifier, and error source is logged)
Per claim 7, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein the semiconductor device is a semiconductor memory (Nemati, [0029] “Memory control circuit 101”) and
information for specifying a type of a corresponding failure included in the third information is returned to the control device in response to the control device accessing the semiconductor memory by designating a physical address included in the third information. (Nemati, [0039] “read to the location in turn causes a UE”)
Per claim 8, Nemati in view of Chang teaches
The evaluation method according to claim 7,
wherein the semiconductor device is a semiconductor memory, (Nemati, [0029] “Memory control circuit 101”)
the type of the failure includes at least one of a write abnormality, a read abnormality, or an erase abnormality in the semiconductor memory, and (Nemati, [0038] “Circuitry 250, in the illustrated embodiment, is configured to handle uncorrectable errors on the write link”)
the control device is configured to control access of the semiconductor memory. (Nemati, [0039] “read to the location in turn causes a UE”)
Per claim 9, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein a correspondence relationship between the state of the defect, the type of the failure, and the location of the failure of the semiconductor device are stored in a first storage device, and a physical location of the semiconductor device corresponding to the location of the failure is stored in a second storage device (Nemati, [0026] “In some embodiments, correctable and uncorrectable errors are also tracked at the source of errors (e.g., in certain processor clusters and their caches). The memory cache controller may aggregate error information and trigger various signals in response to certain thresholds.” The source of errors indicates a separate storage device than the controller device, which is used to store the mapping between the location of the failure and the physical location of the semiconductor device)
Per claim 10, Nemati in view of Chang teaches
The evaluation method according to claim 1,
wherein the first information includes at least one of a defect of a resistance value, a disconnection of a specific wiring, a short circuit, or a leak of a specific wiring. (Nemati, [0024] “In some embodiments, the memory is an LPDDR5 memory that is configured to detect both link errors and on-chip errors.” Link errors may include issues, such as disconnections, with specific wiring)
Per claim 11, Nemati teaches
An evaluation device comprising (FIG. 1):
an acquirer configured to acquire first information indicating a state of a defect of a member in a semiconductor device; ([0071] “track and log correctable and uncorrectable errors” Tracking requires the acquisition of the said information);
… configured to store second information indicating that a physical location of a failure and a type of the failure are associated with the first information; (FIG. 7 Example UE Logger Data Structure 610)
and
a control circuit configured to (FIG. 1):
…
control whether to return fourth information for specifying the type of the failure of the semiconductor device to a control device for controlling the semiconductor device based on an access request from the control device and the third information; and ([0039] “read to the location in turn causes a UE” when a control device tries to access the location in which the corruption has been detected, the uncorrectable error is produced. It is the Examiner’s interpretation that because a distinction is made between uncorrectable error (UE) and a correctable error (CE), the assertion of the uncorrectable error teaches “the type of the failure” in the claim language. Furthermore, since the information is only returned to the control device with the request access, it teaches the “controlling…” clause of the claim limitation)
evaluate an operation of the control device after the fourth information is returned. ([0029] “Memory control circuit 101, in the illustrated embodiment, receives access requests 109 via multiple virtual channels 110.” Any further read/write request from the control device will be received and will be evaluated through the same process)
Nemati fails to teach
a storage device
generate third information including the location of the failure and the type of the failure in the semiconductor device based on the first information and the second information stored in the storage device;
Chang teaches
a storage device (FIG. 1)
generate third information including the location of the failure and the type of the failure in the semiconductor device based on the first information and the second information stored in the storage device; ([0038] “an additional deterioration table Damage_TAB is required, which lists every deteriorated logical address LBA_damaged for future recognition. If the logical address that the host 110 requests to read is listed in in the deterioration table Damage_TAB as a deteriorated logical address LBA_damaged.”)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Nemati with the teaching of Chang in order to teach the use of referring to the table with the error details in order to determine the type of error and the error location because, as stated in Nemati, it is a conventional method in doing so ([0055])
Claim 12-16 recites similar claim limitations as claims 2-6 respectively and thus are rejected for similar reasons.
Claim 18, 19, 20 recites similar claim limitations as claims 7, 8, 10 respectively and thus are rejected for similar reasons
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nemati in view of Chang in further view of Zorn et al (US 9978461 B2).
Per claim 17, Nemati in view of Chang teach
The evaluation device according to claim 16
Nemati in view of Chang fails to teach explicitly
wherein the specific member includes a specific wiring disposed at a specific location of the semiconductor device
However, Zorn teaches
wherein the specific member includes a specific wiring disposed at a specific location of the semiconductor device (col 3, lines 1-2, “Note that the source of an error may in general also exist in the logic or wiring that connects memory cells”)
It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Nemati in view of Chang with the teaching of Zorn in order to teach that the error source can be from specific wiring because it offers one possible implementation of the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST.
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/K.L.R./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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