DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on June 17, 2026.
Response to Amendment
Applicant's submission filed on June 17, 2026 has been entered. Claims 1-2, 8-10 and 16-18 are rejected. Claims 3-7, 11-15 and 19-20 are objected to.
Claim Objections
Claims 9-16 are objected to because of the following informalities: In claim 9 line 18, “from being flushed” should be deleted so that line 18 should read “normal storage area,” as there are two instances of “from being flushed” in lines 17-18. All dependent claims are objected to for having the same deficiency as the claim(s) that they depend on. Appropriate correction is required.
Claim Interpretation
Claims 17-20 are directed to a “computer readable storage medium”, without reciting the computer readable storage medium as being non-transitory. However, since paragraph [0106] of applicant’s originally filed specification gives examples of computer readable storage medium, and provides that the examples “and any other devices configured to store computer programs and any associated data, data files, and data structures in a non-transitory manner” may be used as a computer readable storage medium, then claims 17-20 are interpreted as being limited to a non-transitory computer readable storage medium. Therefore, the computer readable storage medium of claims 17-20 are deemed statutory and does not include transitory signals, since paragraph [0106] of applicant’s originally filed specification limits the computer readable storage medium to non-transitory computer readable storage medium(s). Due to such interpretation, claims 17-20 have not been rejected under 35 USC § 101 regarding transitory signals being a form of computer readable storage medium.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9-10 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (Hereinafter Cheng, U.S. Publication No. 2017/0083441).
Regarding claim 1, Cheng teaches:
A data storage method, comprising:
determining, in response to receiving an Input/Output (IO) request, a data response level associated with the IO request (See [0048] “At 302, the method includes determining, based on characteristics of data to be written to the cache memory, a configuration for a region of the cache memory of the processor.” See [0048] “The determined configuration may include a size of the region, a cache policy to apply to the region, or a location for the region within the cache memory.” See [0043] “When a function is executed by μprocessor core 204, instructions or data associated with the function can be written to L1 cache 206 or memory 118-1 (e.g., L2 cache) for future access. In some cases, the data of a function has particular characteristics with respect to cache access or causes a particular access pattern within L1 cache 206 or memory 118-1.” In response to a write request, a cache policy associated with the write request is determined for a cache region. The cache policy corresponds to the data response level.);
determining, according to the data response level, a storage area associated with storing data to be written corresponding to the IO request (See [0048] “At 302, the method includes determining, based on characteristics of data to be written to the cache memory, a configuration for a region of the cache memory of the processor” See [0051] “At 306, the method includes applying, based on the determined configuration, a cache policy to the allocated address range of the cache memory. In some cases, multiple cache policies are applied to multiple respective regions of the cache memory or a shared cache memory. In such cases, the cache may be implemented as a multi-policy cache for multiple functions. By so doing, a single or shared cache can support multiple caching policies to provide optimized caching for a variety of functions with different information access patterns.” Multiple regions of a cache memory are configured according to a particular cache policy.) in a universal flash storage (UFS) device comprising a high speed buffer and a normal storage area, the high speed buffer comprising a first area, a second area, and a third area (See [0071] “System memory 610 or cache memory 612 may include any suitable type of memory, such as volatile memory (e.g., DRAM or SRAM), non-volatile memory (e.g., Flash),” See Figure 4, in which shared L1 cache 404 comprises a first area Write Back Region 434, a second area Write Through Region 438, and a third area Read Only Region 436. Memory Subsystem 214 corresponds to the claimed normal storage area.); and
writing the data to be written into the determined storage area, wherein the UFS device is configured to write data to any of the first area, the second area, and the third area based on the determined data response level (See Figure 4, in which shared L1 cache 404 comprises a first area Write Back Region 434, a second area Write Through Region 438, and a third area Read Only Region 436. See [0051] “At 306, the method includes applying, based on the determined configuration, a cache policy to the allocated address range of the cache memory.” See [0036] “a single or shared cache can support multiple caching policies to provide optimized caching for a variety of functions with different information access patterns.” Multiple regions of a cache memory are configured according to a particular cache policy.),
wherein the UFS device is configured to flush data stored in the first area into the normal storage area based on a first rule, flush data stored in the second area into the normal storage area based on a second rule, and block data stored in the third area from being flushed into the normal storage area (See Figure 4, in which data stored in the shared L1 Cache 404 may flushed from the Write Back Region 434 according to a write-back rule, flushed from the Write Through Region 438 according to a write-through rule, and not flushed from the Read Only Region 436 as the data in read-only region cannot be modified and thus not flushed back to main storage.),
wherein read and write speeds of the high speed buffer are greater than respective read and write speeds of the normal storage area (See Figure 4, in which the cache memory has higher read and write speeds than the main storage (i.e. memory subsystem 214).), and
wherein the first area, the second area, the third area, and the normal storage area correspond to different data response levels, respectively (See Figure 4, in which the different regions in the cache memory have different data storage policies (i.e. cache policies). The main storage (i.e. memory subsystem) operates on a different memory storage policy than the cache memory.).
Regarding claim 2, Cheng teaches:
The method of claim 1, wherein the determining of the data response level comprises:
determining the data response level based on at least one of a type of a process corresponding to the IO request, a type of the IO request, and IO Operations Per Second (IOPS) of the process (See [0048] “At 302, the method includes determining, based on characteristics of data to be written to the cache memory, a configuration for a region of the cache memory of the processor.” See [0048] “the characteristics of the information to be written include a type of usage, locality of the information, or access bandwidth” See [0045] “The use of each type of cache policy may correspond with a type of data access (e.g., data access pattern) associated with different respective functions.”), wherein
the type of process indicates one of a foreground process, a background process, and a core process (See [0058] “At 502, the method includes determining a function to be performed by a processor core.”), and
the type of the IO request indicates one of a read operation request, a write operation request, and a read & write operation request (See [0062] “At 510, the method includes caching, based on the set attribute, data of the function written to the region of cache memory.”).
Claim 9 and claim 17 are rejected for the same reasons as claim 1. Claim 10 and claim 18 are rejected for the same reasons as claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Park et al. (Hereinafter Park, U.S. Publication No. 2021/0034296).
Regarding claim 8, Park teaches:
The method of claim 1, wherein the high speed buffer includes a single-level cell flash memory and the normal storage area includes a multi-level cell flash memory (See Figure 8 and [0048] “In an exemplary embodiment, each of memory cells corresponding to the turbo write buffer TWB may be used as a single-level cell (SLC). Additionally, each of memory cells corresponding to the user storage UST may be used as a multi-level cell (MLC) such as a triple-level cell (TLC).”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the region-based cache management system of Cheng with the turbo write policy of Park to improve write performance and increase the speed in which data is read (See [0148]-[0149] of Park).
Claim 16 is rejected for the same reasons as claim 8.
Response to Arguments
Applicant's arguments filed June 17, 2026 have been fully considered but they are not persuasive. Applicant’s representative submitted that Cheng does not disclose “wherein the UFS device is configured to write data to any of the first area, the second area, and the third area based on the determined data response level”, because the action relied on Cheng’s read only region 436 in rejecting the third area of the claims. Examiner respectfully disagrees, as under broadest reasonable interpretation of the amended limitation, if any of the regions specified in Cheng are configured to receive write data based on the determined data response level, then the limitation has been met. For example, Figure 4 at least depicts a first area Write Back Region 434 and a second area Write Through Region 438, which are configured according to a particular cache policy and are able to receive write data. Therefore, applicant’s arguments are not persuasive, and the independent claims remain rejected in view of Cheng.
Allowable Subject Matter
Claims 3-7, 11-15 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record failed to teach the totality of the combination of the claimed limitations in each of the dependent claims 3-7, 11-15 and 19-20 respectively, nor would it have been obvious.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
Prosecution Insights