Prosecution Insights
Last updated: April 19, 2026
Application No. 19/061,192

MESH DECODING DEVICE, MESH DECODING METHOD, AND PROGRAM

Non-Final OA §103
Filed
Feb 24, 2025
Examiner
KALAPODAS, DRAMOS
Art Unit
2487
Tech Center
2400 — Computer Networks
Assignee
Kddi Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
562 granted / 713 resolved
+20.8% vs TC avg
Strong +28% interview lift
Without
With
+28.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
34 currently pending
Career history
747
Total Applications
across all art units

Statute-Specific Performance

§101
5.0%
-35.0% vs TC avg
§103
54.4%
+14.4% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 713 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement 2. The information disclosure statement (IDS) was submitted on 02/24/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application does not currently name joint inventors. 3. Claims 1-7, are rejected under 35 U.S.C. 103 as being unpatentable as being obvious over Joerg Muller et al., (hereinafter Muller) “Shading Atlas Streaming”; Graz University of Technology, 2018 in view of Park Jungsun et al., (hereinafter Park) (WO 2023/172509A1). Re Claim 1. Muller discloses, a mesh decoding device comprising a circuit, (decoding at a client unit 6, of Fig.2, atlas frames Sec.3 (5)) wherein the circuit: decodes an atlas bit stream and output patch (outputting patches at the visibility stage, Fig.4 or Fig.6, Sec.3.1, and Sec.4.1) information and frame information (and decoding the video stream, i.e., bitstream, obtained from the network stage (5a) unit 4, and outputs atlas frames (5a) and meta-information (5b) in Fig.2, Sec.3 (5)); changes a subdivision method based on the patch information and the frame information (changing the atlas into subdivided square superblocks into columns of equal width which are further divided into same width blocks with variable height, per Fig.7 Sec.4.1 into “Patches and blocks”, at sub. (1), (2), (3)); and changes an inverse quantization method based on the patch information (according to the dynamic geometry method, the quantized visible vertices applied at compression stage above a certain number e.g., >30, per Sec. 6.5, an inverse quantization is assumed at the decoder side at decompression process). In an analogous art, Park teaches the decoding process of a video mesh bitstream, decodes an atlas bit stream and output patch information and frame information (a mesh decoder 103, Par.[0060] and per Fig.32 receiving a video mesh bitstream as an atlas data sub-bitstream at unit 3206, to be decoded at unit 3208, Abstract and mesh patches in Fig.22 Par.[0027, 00110] being sub-divided based on mesh information Par.[00111], into corresponding patches, per Fig.35 Par.[0040]); changes a subdivision method based on the patch information and the frame information (changing the subdivision counts based on patch information, Par.[00412]); and changes an inverse quantization method based on the patch information (reconstructing the mesh by inverse quantization at unit 1803, based on mesh/patch information, at unit 1808, Fig.18, Par.[0076-0077]). The skilled artisan would have found obvious before the effective filing date of invention to associate the common method of atlas video coding process in Muller, by finding detailed disclosure of the atlas subdivided mesh decoding applied in the art to Kim, while seeking the advantage of mesh subdividing into patches, to be used in the coding process providing for lossless coding for boundary vertices (at Par.[0084]), thus considering such combination predictable. Re Claim 2. Muller and Park disclose, the mesh decoding device according to claim 1, Park teaches that, wherein the circuit calculates a subdivided vertex normal based on a method of calculating the subdivided vertex normal designated for each patch (for each vertex v, indicating a normal vector Nv, Par.[00112]). Re Claim 3. Muller and Park disclose, the mesh decoding device according to claim 1, Park teaches, wherein the circuit adjusts a subdivided mesh based on a subdivision adjustment method designated for each frame (subdivision scheme for mesh for each frame, per Fig.8, or 9 Par.[0057]). Re Claim 4. Muller and Park disclose, the mesh decoding device according to claim 1, Park teaches, wherein the mesh decoding unit includes an inverse quantization unit configured to perform inverse quantization of a displacement based on a quantization value designated for each patch (performing inverse quantization Fig.18, Par.[0076-0077] based on the displacement vector for each vertex corresponding to the subdivided mesh 603 i.e., patches per Fig.6, Par.[0056-0057, 0061]). Re Claim 5. Muller and Park disclose, the mesh decoding device according to claim 1, Park teaches, wherein the circuit performs inverse quantization of a displacement based on a quantization value for each subdivision level designated for each patch (performing inverse quantization by a value of the quantized frame 1001, Par.[0060] at mesh decoder 1003, Fig.17, on canonical coordinates decision made at the frame, patch group or patch level, Par.[0066]). Re Claim 6. This claim represents the mesh decoding method performing each and every limitation of the decoding device of claim 1, hence it is rejected on the same evidentiary premise, mutatis mutandis. Re Claim 7. This claim represents the program stored on a non-transitory computer- readable medium (Kim: at Par.[00450]) for causing a computer to function as a mesh decoding device, according to each and every limitation processed at the apparatus claim 1, hence it is rejected on the same evidentiary premise, mutatis mutandis. Conclusion 4. The prior art made of record and not relied upon, is considered pertinent to applicant's disclosure is listed below. US 2022/0343545; US 11,523,135; US 2025/0173907; US12,3404,68 B2; and WO 2022050688A1. See PTO-892 form. Applicant is required under 37 C.F.R. 1.111(c) to consider these references when responding to this action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DRAMOS KALAPODAS whose telephone number is (571)272-4622. The examiner can normally be reached on Monday-Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Czekaj can be reached on 571-272-7327. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DRAMOS KALAPODAS/Primary Examiner, Art Unit 2487
Read full office action

Prosecution Timeline

Feb 24, 2025
Application Filed
Feb 04, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+28.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 713 resolved cases by this examiner. Grant probability derived from career allow rate.

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