Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
(b) The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
35 U.S.C. 112(b)
Claims 1, 14 and 18 are rejected under 35 U.S.C. 112(b) as indefinite. Each independent claim recites obtaining “a capacity of a first power storage element … based on a difference between the total capacity of the first group … and the total capacity of the second group,” but does not define the relationship among “the first group,” “the second group,” and “the first power storage element.” Because the difference between two arbitrarily-constituted group totals does not, without more, yield the capacity of a particular element, the metes and bounds of the claim are unclear. Dependent claims 2, 15 and 19 resolve this by reciting that the first group is all of the elements and the second group is all of the elements except one. For purposes of examination, the independent claims are interpreted as requiring the first and second groups to differ by the first power storage element. Clarification (e.g., importing the limitation of claims 2/15/19 into the independent claims) is recommended.
Claim Interpretation - 35 U.S.C. 112(f)
The “measurement circuit,” “step-up/down circuit,” “constant current circuit,” and “calculation circuit” limitations have been considered under 35 U.S.C. 112(f) and are not interpreted under 112(f). The term “circuit,” when preceded by appropriate descriptive structure, connotes a class of structures to one of ordinary skill, and the specification discloses corresponding hardware (measurement circuit 32, step-up/down circuit 35, constant current circuit 31, latch circuit 34, and calculation circuit 11; FIG. 1). The “… circuit” limitations are accordingly given their ordinary structural meaning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 13-20 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Yamasaki (“Yamasaki”) (US Pub No. 2022/0084604) in view of Chou et al. (“Chou”) (US Pub No. 2024/0027504).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Yamasaki and Chou references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Yamasaki discloses a power supply management circuit comprising: a terminal connectable to a plurality of power storage elements (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Yamasaki discloses power management circuit (PMIC) 130 with a terminal connected to capacitor 140, which “may comprise a plurality of parallel-connected capacitors”. See ¶ [0021]-[0029];(FIG. 1));
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a measurement circuit configured to measure a voltage of the terminal (in Yamasaki, measurement circuit 20 measures the terminal voltage Vcap of the capacitor. See ¶ [0051]; (FIG. 1; FIG. 6));
and a step-up/down circuit connected to the plurality of power storage elements via the terminal (in Yamasaki, step-up/down circuit 131 charges and discharges the capacitor 140 via the terminal. See ¶ [0085]; (FIG. 1)),
wherein the power supply management circuit is configured to: cause a first group of the power storage elements to be in a connected state to measure a first voltage difference while the first group of the power storage elements are discharged at a first constant current, and obtain a total capacity of the first group of the power storage elements based on the first constant current and the first voltage difference (in Yamasaki, constant current circuit 10 draws constant current Iconst; measurement circuit 20 measures dV over dt; calculation circuit 40 computes Ctotal = Iconst×(dt/dV) for the connected bank. See ¶ [0027]; [0060]-[0065]; (FIG. 5; Eq. 3/8)),
cause a second group of the power storage elements to be in a connected state by turning on the corresponding one or more of the switches, cause the step-up/down circuit to charge the second group of the power storage elements, cause the measurement circuit to measure a second voltage difference while the second group of the power storage elements are discharged at a second constant current, and obtain a total capacity of the second group of the power storage elements based on the second constant current and the second voltage difference (in Yamasaki, constant current circuit 10 draws constant current Iconst; measurement circuit 20 measures dV over dt; calculation circuit 40 computes Ctotal = Iconst×(dt/dV) for the connected bank. See ¶ [0027]; [0060]-[0065]; (FIG. 5; Eq. 3/8)). Yamasaki does not teach: a plurality of switches respectively for the elements. Yamasaki does not teach: selecting a group via switches. Yamasaki does not teach: obtaining an individual element’s capacity by a difference of group totals. In the same field of endeavor, Chou discloses a plurality of switches respectively for the elements (as shown in Fig. 5, which is reproduced below for ease of reference and convenience, Chou discloses a plurality of capacitors (DUTs 51–5N) each connected via respective switches S11–SN4 under controller 14. See ¶ [0051]-[0056]; figure 5),
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selecting a group via switches (in Chou, switch-selecting which capacitors are connected for a measurement (S11–SN4; controller 14. See ¶ [0051]-[0056]; figure 5); obtaining an individual element’s capacity by a difference of group totals (in Chou, isolating an individual capacitance by a difference of two measurement configurations, CDUT = CTOTAL − CPARASITIC. See ¶ [0031]; [0043]).
Yamasaki and Chou are analogous art directed to measuring capacitance of capacitors. Yamasaki measures the total capacitance of a (possibly multi-capacitor) PLP bank but cannot resolve which individual capacitor has degraded - yet Yamasaki is expressly concerned with per-bank degradation because the measured capacitance determines whether the back-up operation can be guaranteed and sets the product life. Chou teaches that, given a plurality of switched capacitors and a controller, an individual capacitance is obtained by differencing two measurement configurations. It would have been obvious to one of ordinary skill before the effective filing date to provide Yamasaki’s parallel PLP capacitors with respective switches and to obtain each element’s capacity by Chou’s difference method (measure the all-element group, measure the all-but-one group, subtract) because: (i) it is a combination of known elements (Yamasaki’s constant-current group-capacitance measurement + Chou’s switched, difference-based isolation of an individual capacitance) according to known methods to yield the predictable result of per-element capacity resolution (KSR rationale (A); MPEP 2143); (ii) it applies a known technique (Chou’s switched differential isolation) to a known device (Yamasaki’s PLP capacitor bank) ready for improvement to yield the predictable result of identifying which specific PLP element has degraded (KSR rationale (C)/(D)); and (iii) it is motivated by Yamasaki’s express goal of monitoring PLP-capacitor degradation to guarantee the back-up operation - resolving per-element capacity lets the system identify, replace, or rest a specific degraded element.
A reasonable expectation of success existed because both references operate a controller that measures terminal voltages of switched capacitors; integrating switch-selected group measurement with constant-current capacitance computation involves only routine circuit design and elementary arithmetic.
In regard to claims 2, 15, 19, Chou discloses wherein the first group is all of the plurality of power storage elements, and the second group is all of the plurality of power storage elements except one (in Chou, isolating one device by the difference between a configuration including all elements (CTOTAL) and a configuration excluding one element (CPARASITIC) (i.e., first group = all; second group = all but one). See ¶ [0041]-[0043]; [0046]-[0049]). A POSITA would have been motivated to combine these references because both are directed to the same technical field (precise capacitance measurement for reliable operation in semiconductor/memory/power circuits) and address the closely related problem of accurately determining capacitance values of power storage elements under real-world conditions (leakage, parasitics, manufacturing variations). Extending Yamasaki’s constant-current/voltage-based measurement in a PLP memory system with the Chou’s switch-based grouping and differential techniques is a predictable improvement that allows individual element monitoring without additional hardware complexity. This yields the expected benefit of better PLP reliability (detecting degraded individual capacitors in multi-element setups) while maintaining compatibility with existing memory system architectures which is a routine optimization in the art of power supply management for storage devices.
In regard to claims 3, 16, 20 Yamasaki discloses wherein each of the plurality of power storage elements is a capacitor, and the obtained capacity of the first power storage element is a capacitance thereof (in Yamasaki, each element is a capacitor and the obtained value is a capacitance (capacitor 140; Ctotal. See ¶ [0027]; [0060]-[0065]).
In regard to claim 4 Yamasaki discloses wherein each of the plurality of power storage elements is a battery (in Yamasaki, the storage element may be a battery (examples of capacitor 140 “includes … a battery”. See ¶ [0025]).
In regard to claims 5, 7, Yamasaki discloses wherein the first group of the power storage elements is charged to a first voltage, and the second group of the power storage elements is charged to a second voltage less than the first voltage (in Yamasaki, charges the bank to an initial voltage V0 before measurement. See ¶ [0039]). Yamasaki does not expressly disclose charging different groups to different (decreasing) voltages. However the teaching of charging different groups to different (decreasing) voltages is a predictable design choice to keep measurements within range; no new function.
In regard to claims 6, 8, Yamasaki discloses wherein the power supply management circuit is further configured to: cause a third group of the power storage elements to be in a connected state by turning on the corresponding one or more of the switches, cause the step-up/down circuit to charge the third group of the power storage elements, cause the measurement circuit to measure a third voltage difference while the third group of the power storage elements are discharged at a third constant current, and obtain a total capacity of the third group of the power storage elements based on the third constant current and the third voltage difference; and obtain a capacity of a second power storage element among the plurality of power storage elements based on a difference between the total capacity of the first group of the power storage elements and the total capacity of the third group of the power storage elements (in Chou, a plurality of switched DUTs enabling additional group measurements; obtaining a second/third element’s capacity by further group differences. See ¶ [0025]; [0031]; [0041]-[0049]; Fig 3). A POSITA would have been motivated to combine Chou with Yamasaki because both references solve the known challenge of accurate, cost-effective capacitance monitoring in power-critical semiconductor systems (PLP in storage devices vs. DUT testing in semiconductor manufacturing). The combination represents the predictable use of known switch/group measurement techniques to enhance individual element visibility in a multi-capacitor PLP setup that is directly improving failure detection and system reliability without undue experimentation or unexpected results. This is the type of iterative improvement routinely made in Kioxia/Toshiba-style memory power management designs.
In regard to claims 13, 17, Yamasaki discloses a memory system comprising: a memory connected to the power supply management circuit (in Yamasaki, a memory system comprising the circuit and a memory (nonvolatile semiconductor memory 120, e.g., NAND). See ¶ [0021]-[0022]).
Independent claims 14 (circuit/system) and 18 (method) recite the same operative limitations as system of claim 1 in system and method form respectively. Chou discloses the plurality of switches positively recited as part of the circuit - Chou’s switches S11–SN4 are part of the measurement system. The method/circuit distinction does not impart patentability where the underlying operative steps are the same. See MPEP § 2114.
Therefore, claims 14 and 18 are rejected on the same basis and mapping as claim 1 above.
Examiner's note:
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: the applied art (Yamasaki and Chou) does not teach or suggest:
• Claim 9/10: a temperature sensor, counting the number of times the first element has been charged/discharged, and obtaining a wear-out degree of the element from its initial capacity, obtained capacity, the counted number, and the measured temperature (and the ratio-with-correction-coefficient computation of claim 10).
• Claim 11/12: obtaining a wear-out degree of each element and selecting a part, but not all, of the elements for use as the PLP power source so as to exclude the most-worn element (wear-leveling selection).
Conclusion
Claims 1-8, 13-20 are rejected. Claims 9-12 are objected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Butler et al. (US Pub No. 2021/0231720) disclose the systems and methods for PLP capacitor health check which is closely related PLP-capacitor monitoring
Hauck et al. (US Pub No. 2012/004445) disclose the measure energy capacity of a backup power supply without compromising power delivery which relates to PLP capacitor capacity measurement.
Cagno et al. (US Pub No. 2010/0052625) disclose the In-situ verification of capacitive power support which is the backup capacitor verification.
Matsuda et al. (US Pub No. 2013/0283069) disclose the storage apparatus with capacitor-backed control which relates to PLP capacitor management.
Kato et al. (US Pub No. 2015/00236530) disclose the semiconductor device for battery control and battery pack which teaches switched per-cell measurement/balancing.
Jaeger et al. (US No. 7,772,803) disclose the flying-capacitor measurement of individual cells among a plurality of series cells via per-cell switches which teaches per-element switched selection (voltage).
Hariharasudhan et al. (US No. 9,625,529) disclose the battery pack management which teaches the per-cell monitoring/selection
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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