DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 7-12 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 7-12 of copending Application No. 19/091,053 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Note that the claimed integrator circuit of reference application will inherently have an integrator circuit path passing a signal through the integrator circuit and a delay locked loop inherently comprises a delay element.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 12 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of copending Application No. 19/091,053 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of the instant application is merely a broad presentation of claim 13 of copending Application No. 19/091,053.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwasniewski et al. (US 7,675,332; “Kwasniewski”).
Regarding claim 7, Kwasniewski teaches a circuit (figure 4) for adjusting signal frequency based upon changes in operational parameters, the circuit comprising:
an integrator circuit path (through CP and integrator 432) configured to generate an output signal (OUT) having an output frequency (inherent property of oscillating signal); and
a delay locked loop (400) configured to adjust a reference signal frequency (Input Clock CLK), the delay locked loop comprising a delay element (111-115) that is configured to offset a phase of the reference signal (CLK) based upon an initial calibration (with control voltage Vtf) such that the reference signal frequency (CLK) matches (according to similar delays 111-115 and 421-424; col. 6, lines 32-40 and 50-53) the output frequency of the output signal (OUT).
As for claim 8, Kwasniewski teaches wherein the integrator circuit path comprises buffering and filtering circuitry (410-420) to remove any harmonics from the reference signal.
Claims 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenyon et al. (US 2020/0336288; “Kenyon”).
Regarding claim 7, Kenyon teaches a circuit (figure 2) for adjusting signal frequency based upon changes in operational parameters, the circuit comprising:
an integrator circuit path (through integrator 237; Kenyon uses integrators for lowpass filters; para. [0027]) configured to generate an output signal (from 232) having an output frequency; and
a delay locked loop (221-223) configured to adjust a reference signal frequency (115), the delay locked loop comprising a delay element (221) that is configured to offset a phase of the reference signal (115) based upon an initial calibration (with control signal 224) such that the reference signal frequency matches (using phase detector 225) the output frequency of the output signal (from 232).
As for claim 8, Kenyon teaches wherein the integrator circuit path comprises buffering and filtering circuitry (111RX) to remove any harmonics from the reference signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwasniewski in view of Stubbs et al. (US 2002/0089361; “Stubbs”).
Regarding claims 9 and 10, Kwasniewski teaches the circuit of claim 7, as detailed above, but fails to teach wherein the circuit is further configured to adjust signal frequency based upon changes in operational temperature; and wherein the delay element is further configured to offset the phase of the reference signal based upon an initial temperature-based circuit calibration.
However, it is well-known to those of ordinary skill in the art to compensate for frequency/phase variations from temperature fluctuations with a delay locked loop. For example, see para. [0014] of Stubbs.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the DLL of Kwasniewski with temperature compensation because such a modification would have provided the well-known benefit of frequency/phase correction from temperature variations.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kwasniewski.
Regarding claim 12, Kwasniewski teaches the circuit of claim 7, as detailed above, but fails to teach wherein the circuit comprises a high-Q circuit configured to resonate at a specific frequency with minimal energy loss over time.
However, it is well-known to those of ordinary skill in the art to utilize hi-q resonating devices in DLLs to reduce power consumption from energy loss.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the DLL of Kwasniewski with a hi-q device because such a modification would have provided the well-known benefit of reducing power consumption from energy loss.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kenyon in view of Cioffi et al. (US 7,449,968; “Cioffi”).
Regarding claims 9 and 10, Kenyon teaches the circuit of claim 7, as detailed above, but fails to teach wherein the circuit is further configured to adjust signal frequency based upon changes in operational temperature; and wherein the delay element is further configured to offset the phase of the reference signal based upon an initial temperature-based circuit calibration.
However, it is well-known to those of ordinary skill in the art to compensate for frequency/phase variations from temperature fluctuations in a PLL. For example, see figure 3 of Cioffi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the PLL of Kenyon with temperature compensation because such a modification would have provided the well-known benefit of frequency/phase correction from temperature variations.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kenyon.
Regarding claim 12, Kenyon teaches the circuit of claim 7, as detailed above, but fails to teach wherein the circuit comprises a high-Q circuit configured to resonate at a specific frequency with minimal energy loss over time.
However, it is well-known to those of ordinary skill in the art to utilize hi-q resonating devices in DLLs to reduce power consumption from energy loss.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the DLL of Kenyon with a hi-q device because such a modification would have provided the well-known benefit of reducing power consumption from energy loss.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Cioffi in view of Ek et al. (US 2020/0014331; “Ek”).
Regarding claim 1, Cioffi teaches a circuit (figure 3) for controlling the output of a frequency resonator, the circuit comprising:
a phase locked loop (316-324) configured to be locked to a reference signal (from MEMS resonator; labeled 300 in figure 3, but labeled as 302 in col. 4, line 41); and
a lock range control (LRC) circuit (306, 338, 330, 328) operably coupled to the PLL (316-324), the LRC circuit comprising a sensor (306) and a limiter (328), wherein the limiter (328) is configured to provide LRC input signal to signal divider circuitry (324) such that an output of the PLL (316-324) stays close to a resonant value of the reference signal (from MEMS 302; Col. 4, line 58 through col. 5, line 16).
Cioffi fails to teach the PLL comprising a time-to-digital convertor.
However, it is well-known to those of ordinary skill in the art to implement a PLL in an analog form or in a digital form including a TDC. For example, see figures 1a and 1b of Ek.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the PLL of Cioffi as a digital PLL including a TDC because such a modification would have been merely exercising a well-known PLL configuration, i.e. a digitally-controlled PLL.
As for claim 2, Cioffi teaches wherein the LRC input signal comprises a temperature-dependent signal (from temp sensor 306).
As for claim 3, Cioffi teaches wherein the sensor comprises a temperature sensor (306).
Regarding claim 4, Cioffi teaches an analog to digital converter (338) to convert an output of the temperature sensor (306) to a digital signal for processing by the signal divider circuitry (324).
Cioffi fails to teach a conditioning circuit to filter the output of the temperature sensor.
However, it is well-known to those of ordinary skill in the art to filter DC control signals to eliminate noise in the control signals.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a conditioning circuit to filter the output of the temperature sensor of Cioffi because such a modification would have provided the benefit of eliminating noise in the temperature sensor signal.
Regarding claim 5, Cioffi teaches wherein the limiter is configured to operate at a frequency range such that an output of the limiter is within an acceptable input range of the signal divider circuitry (Col. 4, lines 58-61).
As for claim 6, Cioffi teaches wherein the circuit comprises a high-Q circuit configured to resonate at a specific frequency with minimal energy loss over time (MEMS 302 is high-q. Col. 1, lines 41-43 and 49-52).
Conclusion
The prior art references made of record and not relied upon teach resonator circuits, comprising: time-to-digital converters, temperature sensors, reference signals, integrator circuits, and delay locked loops.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEVI GANNON/Primary Examiner, Art Unit 2849 February 12, 2026
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