DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/14/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3 and 15-16 are rejected under 35 U.S.C. 102(a1) as being anticipated by Wang et al. (CN 114068590, machine translation, 02-2022) (Wang, hereafter).
Regarding claim 1, Wang discloses (description, paragraphs [0055]-[0123], and figures 2-14) an array substrate 100 and a display panel, the array substrate comprising: a base substrate 101; a gate line 102 and data lines 103 provided on the base substrate 101, wherein the gate line 102 and the data lines 103 cross to define a pixel region 104; and a planarization layer 107, provided on the surface of a first drain 1059 away from the base substrate 101, wherein a via hole structure 1071 is provided in the planarization layer 107, the via hole structure 1071 comprises a first via hole structure 1071a (i.e. the first via hole) and a second via hole structure 1071b (i.e. the second via hole), a first support structure 109 (i.e. the support structure) is provided in a region corresponding to the first via hole structure 1071 a, and a second support structure 110 (i.e. the filling structure) is provided in a region corresponding to the second via hole structure 1071 b (i.e. the second via hole); and the first support structure 109 can be in contact with a spacer column of the color filter substrate included in the display panel, the surface of the first support structure 109 away from the base substrate 101 is recessed towards the side of the base substrate 101, such that when the display panel is subsequently formed, the spacer column on the color filter substrate can be located exactly at the recessed position of the first support structure 109, and the first support structure 109 extends out of the first via hole structure 1071a in a direction perpendicular to a main surface of the base substrate 101. The array substrate further comprises a pixel electrode 108 (i.e. the first electrode), a third electrode 112 (i.e. the second electrode), a portion (i.e. the connection electrode) that enables the first drain 1059 to be in surface contact with the pixel electrode 108, a metal oxide thin film transistor 105 provided in the pixel region 104, a gate 1056, and a channel region which is a region where a metal oxide semiconductor layer 1051 and the first gate 1056 are stacked.
Regarding claim 2, Wang discloses: wherein orthographic projections of the plurality of gate lines on the first base substrate and orthographic projections of the plurality of data lines on the first base substrate have a plurality of overlapping regions, and at least part of the overlapping regions is respectively located in an orthographic projection of a corresponding first via hole on the first base substrate(π17-π18).
Regarding claim 3, Wang discloses: a first light-shielding structure (1053) arranged between a layer where the plurality of gate lines(1056) are located and the first base substrate (100), wherein an orthographic projection of the first light-shielding structure on the first base substrate at least covers an orthographic projection of the first via hole outside a corresponding overlapping region on the first base substrate (π57-π59).
Regarding claim 15, Wang disclose A display panel (Figure 14), comprising: a display substrate and an opposite substrate which are arranged oppositely, wherein the display substrate is the display substrate according to claim 1n(Figure 2), the opposite substrate comprises: a second base substrate (200), and a spacer (no number)arranged on a side of the second base substrate facing the display substrate, wherein an end of a side of the spacer facing the display substrate is arranged in a concave portion of the supporting structure.(π115-π120)
Regarding claim 16, Wang discloses a display apparatus, comprising the display panel according to claim 15 (see rejection claim 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 114068590, machine translation, 02-2022) (Wang, hereafter).
Regarding claims 4-9, Wang fails to explicitly disclose wherein in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole (claim 4); wherein a surface of a side of the supporting structure away from the first base substrate is a first surface, the first surface is of a curved-surface structure, a vertical height difference range between a maximum distance and a minimum distance between the first surface and the first base substrate is a, and 0<|a|≤1 μm.(claim 5); wherein in a cross section perpendicular to the first base substrate, a difference between a maximum radial dimension of the supporting structure and a maximum radial dimension of the filling structure is greater than or equal to 0 μm and smaller than or equal to 5 μm.(claim6); wherein in a cross section perpendicular to the first base substrate, a difference between a maximum radial dimension of the first via hole and a maximum radial dimension of the second via hole is greater than or equal to 2 μm and smaller than or equal to 9 μm(claim 7); wherein in a direction perpendicular to the first base substrate, a depth of the first via hole is greater than a depth of the second via hole(claim 8);wherein in a cross section perpendicular to the first base substrate, a shortest distance S.sub.1 between the first via hole and the second via hole is greater than or equal to 2 μm and smaller than or equal to 5 μm, and a longest distance S.sub.2 between the first via hole and the second via hole is equal to (S.sub.1+h.sub.1*cot β+h.sub.2*cot γ), wherein h.sub.1 is a depth of the first via hole in a direction perpendicular to the first base substrate, β is an angle of gradient of the planarization layer at the first via hole, h.sub.2 is a depth of the second via hole in the direction perpendicular to the first base substrate, and γ is an angle of gradient of the planarization layer at the second via hole(claim 9). It would be obvious to one of ordinary skill before the effective filing date to modify the display substrate of Wang wherein in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole; wherein a surface of a side of the supporting structure away from the first base substrate is a first surface, the first surface is of a curved-surface structure, a vertical height difference range between a maximum distance and a minimum distance between the first surface and the first base substrate is a, and 0<|a|≤1 μm; wherein in a cross section perpendicular to the first base substrate, a difference between a maximum radial dimension of the supporting structure and a maximum radial dimension of the filling structure is greater than or equal to 0 μm and smaller than or equal to 5 μm; wherein in a cross section perpendicular to the first base substrate, a difference between a maximum radial dimension of the first via hole and a maximum radial dimension of the second via hole is greater than or equal to 2 μm and smaller than or equal to 9 μm; wherein in a direction perpendicular to the first base substrate, a depth of the first via hole is greater than a depth of the second via hole(claim 8);wherein in a cross section perpendicular to the first base substrate, a shortest distance S.sub.1 between the first via hole and the second via hole is greater than or equal to 2 μm and smaller than or equal to 5 μm, and a longest distance S.sub.2 between the first via hole and the second via hole is equal to (S.sub.1+h.sub.1*cot β+h.sub.2*cot γ), wherein h.sub.1 is a depth of the first via hole in a direction perpendicular to the first base substrate, β is an angle of gradient of the planarization layer at the first via hole, h.sub.2 is a depth of the second via hole in the direction perpendicular to the first base substrate, and γ is an angle of gradient of the planarization layer at the second via hole the motivation being to provide a ultra high resolution display, and since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claims 10-14, the limitations wherein a transistor arranged between a layer where the adapting electrode is located and the first base substrate, wherein the transistor comprises a gate, and at least part of an orthographic projection of the second via hole on the first base substrate is located in an orthographic projection of the gate on the first base substrate; further comprising: a second light-shielding structure arranged between a layer where the gate is located and the first base substrate(claim 10); wherein the transistor comprises an active layer disposed between the layer where the gate is located and a layer where the second light-shielding structure is located, the active layer comprises a channel region, and an orthographic projection of the channel region on the first base substrate is located in an orthographic projection of the second light-shielding structure on the first base substrate(claim 11); Wherein a first light-shielding structure arranged between a layer where the plurality of gate lines are located and the first base substrate, wherein the first light-shielding structure and the second light-shielding structure are arranged on a same layer, the first light-shielding structure and the second light-shielding structure are independent of each other, or one first light-shielding structure and an adjacent second light-shielding structure are integrated(Claim 12); a connecting structure arranged on a same layer as the supporting structure and the filling structure, wherein the connecting structure is arranged between the supporting structure and the filling structure and is integrated with the supporting structure and the filling structure; and a distance between a surface of a side of the connecting structure away from the first base substrate and the first base substrate is greater than a distance between a surface of a side of the supporting structure or the filling structure away from the first base substrate and the first base substrate claim 13); wherein a second electrode arranged on a side, away from the planarization layer, of the layer where the first electrode is located (claim 14) etc do not appear to contain any additional features which define more than slight constructional changes which come within the scope of the customary (design) practice followed by persons skilled in the art, especially as the advantages thus achieved can be readily contemplated in advance. Alternatively, these limitations are not deemed patentable since the applicant’s disclosure fails to show such limitations to solve any problems or to yield any unobvious advantage that is not within the scope of the teachings applied. Therefore, such limitations would be a matter of design alternative.
It would be obvious to one of ordinary skill before the effective filing date to modify the display substrate of Wang based on the teachings of wang to derive wherein a transistor arranged between a layer where the adapting electrode is located and the first base substrate, wherein the transistor comprises a gate, and at least part of an orthographic projection of the second via hole on the first base substrate is located in an orthographic projection of the gate on the first base substrate; further comprising: a second light-shielding structure arranged between a layer where the gate is located and the first base substrate; wherein the transistor comprises an active layer disposed between the layer where the gate is located and a layer where the second light-shielding structure is located, the active layer comprises a channel region, and an orthographic projection of the channel region on the first base substrate is located in an orthographic projection of the second light-shielding structure on the first base substrate; wherein a first light-shielding structure arranged between a layer where the plurality of gate lines are located and the first base substrate, wherein the first light-shielding structure and the second light-shielding structure are arranged on a same layer, the first light-shielding structure and the second light-shielding structure are independent of each other, or one first light-shielding structure and an adjacent second light-shielding structure are integrated; a connecting structure arranged on a same layer as the supporting structure and the filling structure, wherein the connecting structure is arranged between the supporting structure and the filling structure and is integrated with the supporting structure and the filling structure; and a distance between a surface of a side of the connecting structure away from the first base substrate and the first base substrate is greater than a distance between a surface of a side of the supporting structure or the filling structure away from the first base substrate and the first base substrate; wherein a second electrode arranged on a side, away from the planarization layer, of the layer where the first electrode is located the motivation being to reduces the source electrode structure, so as to improve the aperture opening rate of the pixel, and since design alternative requires only routine skill.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure can be found in the 892 and below:
US 20220005909 A1-General state of the art- display substrate and a manufacturing method thereof, and a display device.
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TRACIE Y. GREEN
Primary Examiner
Art Unit 2875
/TRACIE Y GREEN/Primary Examiner, Art Unit 2875
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