Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Application dated 2/24/2025 claimed priority of date 3/8/2024.
2. Claims 1-16 are presented for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over; the reference claim(s). See, e.g., In re Berg, 140 Fo3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887,225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937,214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms, which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.isp.
3. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of co-pending application 18/742726.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is substantially similar in nature with the Claim limitations of the patent for example
Instant application
Co-pending application 18/742726
1. A method of selection of a boot program for a microprocessor of a microcontroller from among a plurality of boot programs contained in one or more of a plurality of memories of the microcontroller, the method comprising:
1. A method of a selection of a first boot program of a plurality of boot programs, the method comprising:
reading a plurality of registers of the microcontroller during a resetting of the microprocessor; and
reading, during a resetting of a microprocessor, an option register value of an option register that conditions the selection of one of the plurality of boot programs with the option register value, wherein each of the plurality of boot programs is contained in a separate storage memory of a plurality of storage memories; and
selecting, in response to reading of one or more conditions together with a state of at least one signal present on a boot pin of the microcontroller, the boot program.
selecting, in response to reading of the option register value, the first boot program of the plurality of boot programs that is contained in a first storage memory of the plurality of storage memories.
Although the conflicting claims are not identical, they are not patentably distinct from each other because Claim 1 of the instant application is anticipated by claim 1 of the Co-pending application where claim 1 of the Co-pending application contains all the limitations of Claim 1 of the instant application. Therefore, Claim 1 of the instant application is not patently distinct from the earlier filed claim and as such is unpatentable for nonstatutory double patenting.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Munguia et al. (“Munguia”), U.S. Patent Publication No. 2004/0030883.
Regarding Claim 1, Munguia teaches a method of selection of a boot program for a microprocessor of a microcontroller from among a plurality of boot programs contained in one or more of a plurality of memories of the microcontroller [Para: Abstract and Para: 032(“ boot image(s) 512 are stored in data storage device(s) 530 and/or removable storage media 520”)], the method comprising:
reading a plurality of registers [Para: 0023(reading by “Control logic 235 maps device requests 238-244 to device selects 248-254 … Device select values can be implemented in many ways including control bits, counter values, shift registers, light emitting diodes (LED),”)] of the microcontroller during a resetting of the microprocessor [Para: 0026(during “During the subsequent boot process, the fixed address is decoded, again, to produce device request 238. Since the control bit has been incremented to 01, device request 238 maps to device select 250” where the subsequent boot is initiated due to a “reset” as set in para 0025)]; and
selecting, in response to reading of one or more conditions together with a state of at least one signal present on a boot pin of the microcontroller, the boot program [Para: 0026(“Since the control bit has been incremented to 01, device request 238 maps to device select 250. Thus, the computing device performs the boot process based on the bootable information stored in memory device 104” where the device select value corresponds to control value in register as set forth above due to an “event is detected” in para 0046)].
Regarding Claim 15, Munguia teaches microcontroller, comprising a microprocessor (540), a system memory (510), and a user memory (520, 530, 620, 530 etc.), and configured to implement the method of claim 1 [Fig-5-6].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 2-4, 8-9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Munguia as set forth above and Wu et al. (“Wu”), U.S. Patent Application Publication No. 2018/0189496.
Regarding Claim 2, Munguia teaches all limitations of claim 2 as described rejecting Claim 1 above. Munguia does not disclose expressly wherein a first boot program of a system memory of the microcontroller is configured to, when it is selected, implement a configuration of the microprocessor so that it is in a single security mode.
In the same field of endeavor (e.g., secure boot circuitry in a device), Wu teaches wherein a first boot program of a system memory of a microcontroller is configured to, when it is selected, implement a configuration of a microprocessor so that it is in a single security mode [Para: 0015(“SoC to perform either a secure boot operation … at each start or restart of the processor”) and 0018].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Munguia’s teachings of selection of a boot program for a microprocessor of a microcontroller from among a plurality of boot programs contained in one or more of a plurality of memories of the microcontroller with Wu’s teachings of a first boot program of a system memory of a microcontroller is configured to, when it is selected, implement a configuration of a microprocessor so that it is in a single security mode would allow Munguia to prevent attack from hacker during boot time [Para: 0003] and “a malicious image to be loaded into the SoC without the image being authenticated” [Para: 0020].
Regarding Claim 3, Wu teaches wherein the single security mode is a first security mode where, when a non-secure transaction requires access to a secure resource of the microprocessor, an error is returned [Para: 0020(“If a fault-injection attack happens when the processor 212 is at branch point 270, the processor may read an SB bit value of 0 instead of 1, meaning that the processor selects the wrong branch, the non-secure branch 272-276. So a hacker could use a glitch attack to bypass the secure boot process defined by the bootrom code and could cause a malicious image to be loaded into the SoC without the image being authenticated”) and 0024(“SB circuitry 340 includes hardware that triggers the interrupt/reset circuitry 330 to interrupt the processor when the SB bit value is 1 in the SB register 245, which means that the processor is executing non-secure boot instructions in error”)].
Regarding Claim 4, Wu teaches wherein, in the first security mode, when a secure transaction requires access to a non-secure resource of the microprocessor, then an error is returned [Para: 0020(“If a fault-injection attack happens when the processor 212 is at branch point 270, the processor may read an SB bit value of 0 instead of 1, meaning that the processor selects the wrong branch, the non-secure branch 272-276. So a hacker could use a glitch attack to bypass the secure boot process defined by the bootrom code and could cause a malicious image to be loaded into the SoC without the image being authenticated”) and 0024(“SB circuitry 340 includes hardware that triggers the interrupt/reset circuitry 330 to interrupt the processor when the SB bit value is 1 in the SB register 245, which means that the processor is executing non-secure boot instructions in error … non-secure boot instruction in error”)].
Regarding Claim 8, Wu teaches wherein at least one application is executable from a user memory (OTP 217) of the microcontroller, different from the system memory and configured with a first security mode, after a selection of the first boot program [0017(processor executing image validation application in OTP 217 during secure mode)].
Regarding Claim 9, Munguia teaches wherein the system memory is a read- only memory or a memory configured to operate as a read-only memory [Para; 0030(ROM)].
Regarding Claim 16, Since it is directly related to Claim 1 (according to the Examiner’s interpretation), the supporting rationale of the rejection to Claim 1 applies equally as well to Claim 16 and Munguia furthermore teaches and a value of the second register defines a life-cycle state of the microcontroller [Para: 0037(event agent value represent life-cycle)].
Wu teaches a value of the first register defines whether a partitioning of the microprocessor is implemented [Fig-3B(at 270)].
6. Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Munguia and Wu (hereinafter “Munguia-Wu”) and Schwarz et al. (“Schwarz”), U.S. Patent No. 5293610.
Regarding Claim 10, Munguia-Wu teaches selecting, at an initialization of a system, the first boot program from the system memory if: a first register has a first value; a second register has a second or a third value; and the signal present on the boot pin is in a first state as set forth above. Monguia-Wu does not disclose expressly wherein the first value, second value, third value are stored in an option Register.
In the same field of endeavor (e.g., option resister utilized in boot process), Schwarz teaches an option register storing a value [col-3 lines: 35-36(The option register 10 comprise s one byte”) and Fig-1(10)]
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Munguia-Wu teachings of reading a plurality of registers for a boot with Schwarz’s teachings of an option register storing a value would allow Monguia-Wu to enhance efficiency, speed and custom control without effecting main code execution.
Regarding Claim 11, Munguia-Wu teaches selecting, at the initialization of the system, a second boot program from the system memory if: the first register has the first value; the second register has a second value; and the signal present on the boot pin is in a second state [Para: 0023(reading by “Control logic 235 maps device requests 238-244 to device selects 248-254 … Device select values can be implemented in many ways including control bits, counter values, shift registers …” and 0026(“Since the control bit has been incremented to 01, device request 238 maps to device select 250. Thus, the computing device performs the boot process based on the bootable information stored in memory device 104”)].
Schwarz teaches an option resister as set forth above.
Regarding Claims 12-14, These recite different aspects of reading different resister values during boot process which is stored in option resister. One of ordinary skill in the art would utilize the option resister to manipulate the numbers for different boot programs in order to satisfy user requirement and achieving commercial success.
Allowable Subject Matter
7. Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
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