DETAILED ACTION
This action is in response to the Application filed on 02/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/24/2025 and 07/30/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein at least a second phase transistor outputs to a primary inductor corresponding to one of the secondary inductors”. It is unclear what its output from the second phase transistor.
Claim 12 recites “wherein at least a second phase transistor outputs to a primary inductor corresponding to one of the secondary inductors”. It is unclear what its output from the second phase transistor.
Claims 2 – 3 and 13 recite similar limitations and are also rejected.
Claims 4 – 11, 14 – 19 depend(s) directly or indirectly from claims 1 – 3 and 12 – 13 and therefore, are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1 – 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over
US Pub. No. 2023/0049859; (hereinafter Capetillo) in view of US Pub. No. 2022/0109368; (hereinafter Zhou) and further in view of US Pub. No. 2025/0062678; (hereinafter Venkatraman).
Regarding claim 1, Capetillo [e.g. Fig. 3] discloses a Trans-Inductor Voltage Regulator (TLVR), comprising: a plurality of phases, each of the plurality of phases comprising a transistor [e.g. M1] receiving an input voltage [e.g. VIN]; and wherein at least a second phase transistor [e.g. M1 of 302] outputs to a primary inductor [e.g. Lo at 321] corresponding to one of the secondary inductors.
Capetillo fails to disclose wherein a first phase transistor outputs to a plurality of secondary inductors, each of the secondary inductors corresponding to a respective phase; and wherein winding currents through each primary inductor and corresponding secondary inductor are balanced.
Zhou teaches wherein a first phase transistor [e.g. Q1] outputs to a plurality of secondary inductors [e.g. 221-22N-1; outputs a ground voltage], each of the secondary inductors corresponding to a respective phase [e.g. 221-1 corresponding to phase 121, 222-1 corresponding to phase 122 and 22N-1 corresponding to phase N].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein a first phase transistor outputs to a plurality of secondary inductors, each of the secondary inductors corresponding to a respective phase as taught by Zhou in order of being able to provide light load efficiency improvement, paragraph 080.
Venkatraman [e.g. Fig. 2] teaches wherein winding currents through each primary inductor [e.g. windings directly connected to 204, 206,…, 208] and corresponding secondary inductor [e.g. windings 214, 216,..,218] are balanced [e.g. paragraphs 028 – 029 recite “The increase in the primary current in a phase causes the secondary current in that respective phase to increase. The secondary current in all the phases increases when the current in any respective phase increases because the secondaries of all the phases are connected together in a single loop. As the current in the secondary of each respective transformer increases, that secondary current is reflected to the primary side of the transformer in each respective phase. Because the secondaries of all the transformers are connected together, that secondary current is reflected to each respective primary in all of the phases. So, a current increase in the secondary of any transformer increases the current in the primaries of the transformers in all the phases”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein winding currents through each primary inductor and corresponding secondary inductor are balanced as taught by Venkatraman in order of being able to provide improve transient response, paragraph 030.
Regarding claim 2, Capetillo [e.g. Fig. 3] discloses a compensation inductor [e.g. Lc].
Capetillo fails to disclose wherein the first phase outputs to the compensation inductor.
Zhou teaches wherein the first phase [e.g. Q1] outputs [e.g. ground voltage] to the compensation inductor [e.g. Lc].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein the first phase outputs to the compensation inductor as taught by Zhou in order of being able to provide light load efficiency improvement, paragraph 080.
Regarding claim 3, Capetillo [e.g. Fig. 3] discloses wherein the compensation inductor [e.g. Lc] outputs to each of the secondary inductors in series [e.g. 331-332, Tn].
Regarding claim 4, Capetillo [e.g. Fig. 3] discloses wherein an output of the secondary inductors [e.g. upper terminal of 321, 322 and Lo] and an output of the primary inductors [e.g. Lower terminal of Tn] are provided to a same output node [e.g. VOUT].
Regarding claim 5, Capetillo [e.g. Fig. 3] discloses wherein the transistor comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET) [e.g. paragraph 025 recites “Each of the switches M1 and M2 may be a Metal-Oxide-Semiconductor Field-Effect transistor (MOSFET)”].
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Capetillo in view of Zhou, Venkatraman and further in view of US Pub. No. 2026/0262167; (hereinafter Liu).
Regarding claim 6, Capetillo wherein two or more phases are grouped.
Liu [e.g. Fig. 1] teaches wherein two or more phases are grouped [e.g. grouped in Module 110 and Module 120].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein two or more phases are grouped as taught by Liu in order of being able to provide a package with a compact size.
Claim(s) 12 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Capetillo in view of US Pub. No. 2025/0062695; (hereinafter Narula), and further in view of Zhou and Venkatraman.
Regarding claim 12, Capetillo [e.g. Fig. 3] discloses a processing device, the processing device comprising: a Trans-Inductor Voltage Regulator (TLVR), comprising: a plurality of phases, each of the plurality of phases comprising a transistor [e.g. M1] receiving an input voltage [e.g. VIN]; and wherein at least a second phase transistor [e.g. M1 of 302] outputs to a primary inductor [e.g. Lo at 321] corresponding to one of the secondary inductors.
Capetillo fails to disclose a processing unit; a printed circuit board (PCB) in communication with the processing unit; wherein a first phase transistor outputs to a plurality of secondary inductors, each of the secondary inductors corresponding to a respective phase; wherein winding currents through each primary inductor and corresponding secondary inductor are balanced.
Narula [e.g. Fig. 1] teaches a processing unit [e.g. 118]; a printed circuit board (PCB) in communication with the processing unit [e.g. paragraph 023 recites “The transformers 108a-108c can also be discrete components in some examples, and 106, 108, 114, and 118 can be arranged on a printed circuit board (PCB) or other package and can be operably coupled by conductive traces on the PCB”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by a processing unit; a printed circuit board (PCB) in communication with the processing unit as taught by Narula in order of being able to provide control to a voltage regulator in a compact size.
Zhou teaches wherein a first phase transistor [e.g. Q1] outputs to a plurality of secondary inductors [e.g. 221-22N-1; outputs a ground voltage], each of the secondary inductors corresponding to a respective phase [e.g. 221-1 corresponding to phase 121, 222-1 corresponding to phase 122 and 22N-1 corresponding to phase N].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein a first phase transistor outputs to a plurality of secondary inductors, each of the secondary inductors corresponding to a respective phase as taught by Zhou in order of being able to provide light load efficiency improvement, paragraph 080.
Venkatraman [e.g. Fig. 2] teaches wherein winding currents through each primary inductor [e.g. windings directly connected to 204, 206,…, 208] and corresponding secondary inductor [e.g. windings 214, 216,..,218] are balanced [e.g. paragraphs 028 – 029 recite “The increase in the primary current in a phase causes the secondary current in that respective phase to increase. The secondary current in all the phases increases when the current in any respective phase increases because the secondaries of all the phases are connected together in a single loop. As the current in the secondary of each respective transformer increases, that secondary current is reflected to the primary side of the transformer in each respective phase. Because the secondaries of all the transformers are connected together, that secondary current is reflected to each respective primary in all of the phases. So, a current increase in the secondary of any transformer increases the current in the primaries of the transformers in all the phases”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein winding currents through each primary inductor and corresponding secondary inductor are balanced as taught by Venkatraman in order of being able to provide improve transient response, paragraph 030.
Regarding claim 13, Capetillo [e.g. Fig. 3] discloses a compensation inductor [e.g. Lc].
Capetillo fails to disclose wherein the first phase outputs to the compensation inductor.
Zhou teaches wherein the first phase [e.g. Q1] outputs [e.g. ground voltage] to the compensation inductor [e.g. Lc].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein the first phase outputs to the compensation inductor as taught by Zhou in order of being able to provide light load efficiency improvement, paragraph 080.
Regarding claim 14, Capetillo [e.g. Fig. 3] discloses wherein the compensation inductor [e.g. Lc] outputs to each of the secondary inductors in series [e.g. 331-332, Tn].
Regarding claim 15, Capetillo [e.g. Fig. 3] discloses wherein an output of the secondary inductors [e.g. upper terminal of 321, 322 and Lo] and an output of the primary inductors [e.g. Lower terminal of Tn] are provided to a same output node [e.g. VOUT].
Regarding claim 16, Capetillo [e.g. Fig. 3] discloses wherein the transistor comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET) [e.g. paragraph 025 recites “Each of the switches M1 and M2 may be a Metal-Oxide-Semiconductor Field-Effect transistor (MOSFET)”].
Claim(s) 12 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Capetillo in view of Narula, Zhou, Venkatraman and further in view of Liu.
Regarding claim 17, Capetillo wherein two or more phases are grouped.
Liu [e.g. Fig. 1] teaches wherein two or more phases are grouped [e.g. grouped in Module 110 and Module 120].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Capetillo by wherein two or more phases are grouped as taught by Liu in order of being able to provide a package with a compact size.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 7 – 11 and 18 – 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 7 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “for phases within a group, secondary inductor windings are wrapped around two or more posts”.
The primary reason for the indication of the allowability of claim 18 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “for phases within a group, secondary inductor windings are wrapped around two or more posts”.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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