DETAILED ACTION
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 has a ‘;’ at the end of claim instead of a (.) [Wingdings font/0xE0] i.e., an ending period is missing. Correction is required.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 7 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,261,620. This is a statutory double patenting rejection.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 and 8-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,261,620. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced in a table below here for comparison.
Claim No.: __ of application 19/061,704
Claim No.: __ of U.S.P. 12,261,620
1. A device comprising: capacitive digital to analog converter (C-DAC) circuitry including switches configured to transition between an open state and a closed state responsive to switch signals; and controller circuitry configured to provide the switch signals to cause the C-DAC circuitry to: configure the switches into a first configuration to sample a differential analog input signal; configure the switches into a second configuration to convert the sample into a digital value; and configure the switches into a third configuration to discharge a capacitor in the C-DAC circuitry;
(examiner’s note: underlined features of patented claim 1)
1. A device comprising: capacitive digital to analog converter (C-DAC) circuitry including switches configured to transition between an open state and a closed state responsive to switch signals; and controller circuitry configured to provide the switch signals to cause the C-DAC circuitry to: configure the switches into a first configuration to sample a differential analog input signal, wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state; configure the switches into a second configuration to convert the sample into a digital value, wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state; configure the switches into a third configuration to discharge a capacitor in the C-DAC circuitry, wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state; configure the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to the first configuration; configure the switches into a fifth configuration to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration; configure the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to the second configuration; and perform an AZ decision with the switches in the sixth configuration.
2. The device of claim 1, wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state.
“…wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state” of patented of claim 1.
3. The device of claim 2 wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state.
“…wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state” of patented claim 1.
4. The device of claim 3 wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state.
“…wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state” of patented claim 1.
5. The device of claim 4 configure the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to the first configuration.
“…configure the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to the first configuration” of patented claim 1.
6. The device of claim 5 configure the switches into a fifth configuration to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration.
“…configure the switches into a fifth configuration to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration” of patented claim 1.
8. An apparatus comprising: first analog to digital converter (ADC) circuitry, the first ADC circuitry to include: capacitive digital to analog converter (C-DAC) circuitry including a switches, respective ones of the switches configured to transition between an open state and a closed state based on a switch signals; and controller circuitry configured to provide the switch signals to cause the C-DAC circuitry to: configure the switches into a first configuration to sample a differential analog input signal; configure the switches into a second configuration to convert the sample into a digital value; and configure the switches into a third configuration to discharge a capacitor in the C-DAC circuitry.
(examiner’s note: underlined features of patented claim 8).
8. An apparatus comprising: first analog to digital converter (ADC) circuitry, the first ADC circuitry to include: capacitive digital to analog converter (C-DAC) circuitry including a switches, respective ones of the switches configured to transition between an open state and a closed state based on a switch signals; and controller circuitry configured to provide the switch signals to cause the C-DAC circuitry to: configure the switches into a first configuration to sample a differential analog input signal, wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state; configure the switches into a second configuration to convert the sample into a digital value, wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state; configure the switches into a third configuration to discharge a capacitor in the C-DAC circuitry, wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state; configure the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to the first configuration; configure the switches into a fifth configuration to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration; configure the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to the second configuration; and perform an AZ decision with the switches in the sixth configuration; digital to analog converter (DAC) circuitry configured to convert the first set of digital bits to an analog voltage; and second ADC circuitry configured to: receive a difference between the differential analog input signal and the analog voltage; and convert the difference into a second set of digital bits, the second set corresponding to the least significant bits of a digital value.
9. The apparatus of claim 8 wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state.
“…wherein configuring switches into a first configuration includes: (a) a transition of a first switch and a second switch to the closed state, and (b) a transition of a third switch to the open state” of patented claim 8.
10. The apparatus of claim 9 wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state.
“…wherein configuring switches into a second configuration includes: (a) a transition of the first switch and the second switch to the open state, and (b) a transition of the third switch to the closed state” of the patented claim 8.
11. The apparatus of claim 10 wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state.
“…wherein configuring switches into the third configuration includes a transition of the first switch and the second switch to the closed state, wherein configuring switches into the third configuration begins an Auto Zero (AZ) phase with the third switch in the closed state” of patented claim 8.
12. The apparatus of claim 11 wherein the controller circuitry is configured to provide the switch signals to cause the C-DAC circuitry to repeat the transition of the third switch to the open state corresponding to the first configuration.
“…configure the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to the first configuration” of patented claim 8.
13. The apparatus of claim 12 wherein the controller circuitry is configured to provide the switch signals to cause the C-DAC circuitry to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration.
“…configure the switches into a fifth configuration to repeat the transition of the first switch and the second switch to the open state corresponding to the second configuration” of patented claim 8.
14. The apparatus of claim 13 wherein the controller circuitry is configured to provide the switch signals to cause the C-DAC circuitry to repeat the transition of the third switch to the closed state corresponding to the second configuration.
“…configure the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to the second configuration” of patented claim 8.
15. The apparatus of claim 12 perform an AZ decision.
“… perform an AZ decision” of the patented claim 8.
16. The apparatus of claim 8 further including digital to analog converter (DAC) circuitry configured to convert a first set of digital bits to an analog voltage.
“…digital to analog converter (DAC) circuitry configured to convert the first set of digital bits to an analog voltage” of patented claim 8.
17. The apparatus of claim 16 further including a second ADC circuitry configured to: receive a difference between a differential analog input signal and the analog voltage; and convert the difference into a second set of digital bits.
“…second ADC circuitry configured to: receive a difference between the differential analog input signal and the analog voltage; and convert the difference into a second set of digital bits” of patented claim 8.
18. The apparatus of claim 17, wherein the C-DAC circuitry further includes: a first portion of circuit elements, the first portion to include a first half of the switches; a second portion of circuit elements, the second portion to include a second half of the switches, the second portion to mirror the first portion; a positive terminal of a comparator circuit coupled to the first portion of circuit elements; and a negative terminal of a comparator circuit coupled to the second portion of circuit elements.
9. The apparatus of claim 8, wherein the C-DAC circuitry further includes: a first portion of circuit elements, the first portion to include a first half of the switches; a second portion of circuit elements, the second portion to include a second half of the switches, the second portion to mirror the first portion; a positive terminal of a comparator circuit coupled to the first portion of circuit elements; and a negative terminal of a comparator circuit coupled to the second portion of circuit elements.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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