DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
The claim for priority from US Provisional 63/569,335 filed on 25 March 2024 is duly noted.
Claim Objections
Claims 1 and 13 are objected to because of the following informalities:
In claim 1, line 8: “attacks? generated” is unclear;
In claim 13, lines 1-2: “the host” lacks antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 7, 8, 12-15, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sobel et al. (US Patent 10,528,736 B1 and Sobel hereinafter).
As to claim 1, Sobel discloses a system and method for detecting preparatory-stages of rowhammer attacks, the system and method having:
a memory comprising a memory cell array configured to store data (col. 5, lines 1-2; 140, Figure 1) and a logging logic circuit configured to generate a log of detected faults or attacks on the memory cell array (col. 5, lines 1-2; col. 9, lines 37-45; Figures 1-2, 5);
a host hosting a hypervisor, wherein the hypervisor is configured to host a virtual machine, including managing data allocation for processes of the virtual machine to a first region of the memory cell array, wherein the hypervisor is configured to receive the log of detected faults or attacks? generated by the logging logic circuit, wherein, in response to a determination that the first region of the memory cell array has a detected fault or attack based on the log of detected faults or attacks, re-direct data allocation for the virtual machine to a second region of the memory cell array (col. 2, lines 58-61; col. 5, lines 58-59; col. 9, lines 28-32; claim 16; Figures 1-2).
As to claims 8 and 15, Sobel discloses:
a connection to hypervisor hosted on a host computing device (col. 2, lines 58-61; Figures 2, 5);
a memory cell array comprising a plurality of regions configured to store data (col. 5, lines 1-2; 140, Figure 1);
a logging logic circuit configured to generate a log of detected faults or attacks on the memory cell array and to provide the log of detected faults or attacks to the hypervisor via the connection (col. 9, lines 37-45; Figures 2, 5);
a remediation logic circuit configured to restrict access to a region of the plurality of regions of the memory cell array by processes of a virtual machine hosted on the hypervisor in response to a command provided by the hypervisor based on the log of detected faults or attacks (col. 2, lines 58-61; col. 5, lines 58-59; col. 9, lines 28-32; col. 10, lines 2-7; claim 16; Figures 1-2).
As to claim 4, Sobel discloses:
a controller coupled between the host and the memory, wherein the controller is configured to facilitate communication between the hypervisor and the memory for the data allocation for the processes of the virtual machine (col. 11, lines 36-39; Figure 6).
As to claims 12 and 18, Sobel discloses;
wherein the memory is coupled directly to a controller to receive the command from the hypervisor (col. 11, lines 36-39; Figure 6).
As to claims 5, 13, and 19, Sobel discloses:
wherein the controller is coupled to the host via a peripheral component interconnect express bus (col. 11, lines 31-35; Figure 6).
As to claims 7, 14, and 20, Sobel discloses:
wherein the logging logic circuit is configured to generate an entry in the log of detected faults or attacks based on an ECC fault, detection that a wrong encryption key was used, a bit flip, or any combination thereof (claim 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 9, 10, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sobel as applied to claims 1, 8, and 15 above, and further in view of Bains et al. (US 2014/0095780 A1 and Bains hereinafter).
As to claims 2, 9, and 16, Sobel fails to specifically disclose:
wherein the memory includes a remediation logic circuit configured to, in response to a determination that a row of the memory cell array has a detected row hammer attack based on the log of detected faults or attacks from the logging logic circuit, cause a refresh of the row of the memory cell array.
Nonetheless, this feature is well known in the art and would have been an obvious modification of the teachings disclosed by Sobel, as taught by Bains.
Bains discloses a system and method for distributed row hammer tracking, the system and method having:
wherein the memory includes a remediation logic circuit configured to, in response to a determination that a row of the memory cell array has a detected row hammer attack based on the log of detected faults or attacks from the logging logic circuit, cause a refresh of the row of the memory cell array (claims 18, 19).
Given the teaching of Bains, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the teachings of Sobel with the teachings of Bains by performing a refresh. Bains recites motivation by disclosing that refreshing the row provides an active runtime mechanism to monitor and address row hammer events (0023). It is obvious that the teachings of Bains would have improved the teachings of Sobel by performing a refresh in order to monitor and address row hammer events.
As to claim 3, Sobel discloses:
wherein the remediation logic circuit is further configured to restrict access to the first region by processes of the virtual machine based on information provided to the memory by the hypervisor (col. 10, lines 3-7; Figure 1).
As to claim 10, Sobel fails to specifically disclose:
a refresh circuit configured to perform the refresh of the row of the memory cell array based on a refresh command from the remediation logic.
Nonetheless, this feature is well known in the art and would have been an obvious modification of the teachings disclosed by Sobel, as taught by Bains.
Bains discloses:
a refresh circuit configured to perform the refresh of the row of the memory cell array based on a refresh command from the remediation logic (claims 18, 19).
Given the teaching of Bains, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the teachings of Sobel with the teachings of Bains by performing a refresh. Please refer to the motivation recited above with respect to claims 2, 9, and 16 as to why it is obvious to apply the teachings of Bains to the teachings of Sobel.
Claim(s) 6, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sobel as applied to claims 1, 8, and 15 above, and further in view of Lim et al. (US 2012/0210042 A1 and Lim hereinafter).
As to claims 6, 11, and 17, Sobel fails to specifically disclose:
wherein the hypervisor is configured to determine a third region of the memory cell array has a fewest number of logged faults based on the log of detected faults or attacks and to direct data allocation for a second virtual machine to the third region of the memory cell array.
Nonetheless, this feature is well known in the art and would have been an obvious modification of the teachings disclosed by Sobel, as taught by Lim.
Lim discloses a system and method for remote memory for virtual machines, the system and method having:
wherein the hypervisor is configured to determine a third region of the memory cell array has a fewest number of logged faults based on the log of detected faults or attacks and to direct data allocation for a second virtual machine to the third region of the memory cell array (0016, lines 4-8; 0017, lines 14-18).
Given the teaching of Lim, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the teachings of Sobel with the teachings of Lim by direct data allocation to another region. Lim recites motivation by disclosing that directing data allocation to a different region provides balance between performance and free local memory (0016). It is obvious that the teachings of Lim would have improved the teachings of Sobel by directing data allocation to a different region in order to provide balance.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Agarwal et al. (US 2023/0385206 A1) discloses a system and method for detecting and mitigating memory attacks.
Chrabaszcz (US Patent 6,363,497 B1) discloses a system and method for clustering software applications.
Foreman et al. (CN 103116570 A) discloses a system and method for distributed computing architecture with reconfigurable hypervisor nodes.
Gauthier et al. (US 2026/0044595 A1) discloses a system and method for attack detection.
Gurumurthi et al. (US 2023/0195889 A1) discloses a system and method for software-level containment of row hammer attacks.
Kasturi et al. (US 2015/0341377 A1) discloses a system and method for providing real-time cloud security.
Levin et al. (US Patent 10,664,590 B2) discloses a system and method for filesystem action profiling of containers and security enforcement.
Lu et al. (US 2025/0131973 A1) discloses a system and method for logging a memory address associated with faulty usage-based disturbance data.
Nagafuchi et al. (WO 2016/035644 A1) discloses a system and method for control.
Poornachandran et al. (EP 3382593 B1) discloses a system and method for security monitoring agent.
Schulz et al. (CN 100451995 C) discloses a system and method for keeping cache of virtual machine.
Vasudeva et al. (US 2021/0334374 A1) discloses a system and method for protecting against malware attacks.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH SU whose telephone number is (571)270-3835. The examiner can normally be reached 6:30 AM - 3:00 PM.
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/SARAH SU/Primary Examiner, Art Unit 2431
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