DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-17 are presented for examination.
Drawings
The drawings submitted 05/04/2007 are objected to because:Figure 1 needs a "Prior Art" label.
A proposed drawing correction or corrected drawings are required in reply to the office action to avoid abandonment of the application. The objection to the drawings will not be held in abeyance.
Corrected drawings sheets in compliance with 37 CFR 1.121(d) are required in reply to the office action should include all the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended”. If a drawing figure is to be cancelled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheet may be necessary to show the renumbering of the remaining figures. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header so as not to obstruct any portion of the drawing figures. If the changes are not acceptable by the examiner, the applicant will be notified and informed of any required corrective action in the next office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-17 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-40 of (U.S. PN: 12,242,759), (U.S. PN: 11,954,363), and (U.S. PN: 11,301,172).
For example, claim 2 of the present application teaches “A memory module, comprising a first memory device comprising a first memory controller and a first plurality of memory circuits, the first memory controller and the memory circuits each being provided on a semiconductor die, each semiconductor die being bonded to another one of the semiconductor dies, wherein each memory circuit comprises (i) one or more three-dimensional memory arrays; and (ii) a plurality of interconnect conductors which communicate data and control signals between the first memory controller and the memory circuit, the data and control signals being associated with reading, writing or erasing of the three-dimensional memory arrays; and the first memory controller comprising a first interface circuit implementing a first data transfer protocol and a second interface circuit implementing a second data transfer protocol, the second data transfer protocol having a higher data transfer bandwidth than the first data transfer protocol, wherein the first memory controller receives over the first interface circuit transactions issued by a first host processor to be carried out by the first memory controller, and the first memory controller receives over the second interface circuit transactions issued by a second host processor to be carried out by the first memory controller, the first and second host processors storing data in the one or more three-dimensional memory arrays of the first plurality of memory circuits, the stored data to be accessed by the first host processor and the second host processor over respective first and second interface circuits” Whereas claim 1 of (U.S. PN: 12,242,759) “A memory module, comprising: an internal bus; a first memory-mapped device coupled to the internal bus, the first memory-mapped device comprising a controller and a plurality of memory circuits, the controller and the memory circuits each being provided on a semiconductor die, each semiconductor die being bonded to another one of the semiconductor dies, wherein each memory circuit comprises (i) one or more three-dimensional memory arrays; and (ii) a plurality of interconnect conductors which communicate data and control signals between the controller and the memory circuit, such data and control signals being associated operations of the memory circuit; and a second memory-mapped device coupled to the internal bus, wherein the internal bus communicates data and control signals between the controller and the second memory-mapped device, such data and control signals being associated with the operations of the second memory-mapped device”
The examiner would like to point out that claim 2 of the present application is substantially the same of claim 1 of (U.S. Patent No. 12,242,759). One is just an embodiment of the other and also the claims are obvious variations of each other and not patentably distinct.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Dependent claims of the instant application are deemed obvious over the dependent claims U.S. patent no. 12,242,759 for the same rationales discussed above.
For example, claim 2 of the present application teaches “A memory module, comprising a first memory device comprising a first memory controller and a first plurality of memory circuits, the first memory controller and the memory circuits each being provided on a semiconductor die, each semiconductor die being bonded to another one of the semiconductor dies, wherein each memory circuit comprises (i) one or more three-dimensional memory arrays; and (ii) a plurality of interconnect conductors which communicate data and control signals between the first memory controller and the memory circuit, the data and control signals being associated with reading, writing or erasing of the three-dimensional memory arrays; and the first memory controller comprising a first interface circuit implementing a first data transfer protocol and a second interface circuit implementing a second data transfer protocol, the second data transfer protocol having a higher data transfer bandwidth than the first data transfer protocol, wherein the first memory controller receives over the first interface circuit transactions issued by a first host processor to be carried out by the first memory controller, and the first memory controller receives over the second interface circuit transactions issued by a second host processor to be carried out by the first memory controller, the first and second host processors storing data in the one or more three-dimensional memory arrays of the first plurality of memory circuits, the stored data to be accessed by the first host processor and the second host processor over respective first and second interface circuits” Whereas claim 1 of (U.S. PN: 11954363) “A memory module, comprising: a first semiconductor die, having formed thereon a first set of one or more three-dimensional memory arrays (“3-D memory arrays”) and a first group of interconnect conductors for sending and receiving data and control signals associated with reading, writing or erasing of the 3-D memory arrays; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die having formed thereon a memory controller including an internal bus connecting the memory controller and the first set of 3-D memory arrays through the first group of interconnection conductors, and wherein the memory controller sends and receives the data and control signals to access the first set of 3-D memory arrays during reading, writing or erasing operations”.
The examiner would like to point out that claim 2 of the present application is substantially the same of claim 1 of (U.S. Patent No. 11,954,363). One is just an embodiment of the other and also the claims are obvious variations of each other and not patentably distinct.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Dependent claims of the instant application are deemed obvious over the dependent claims U.S. patent no. 11,954,363 for the same rationales discussed above.
For example, claim 2 of the present application teaches “A memory module, comprising a first memory device comprising a first memory controller and a first plurality of memory circuits, the first memory controller and the memory circuits each being provided on a semiconductor die, each semiconductor die being bonded to another one of the semiconductor dies, wherein each memory circuit comprises (i) one or more three-dimensional memory arrays; and (ii) a plurality of interconnect conductors which communicate data and control signals between the first memory controller and the memory circuit, the data and control signals being associated with reading, writing or erasing of the three-dimensional memory arrays; and the first memory controller comprising a first interface circuit implementing a first data transfer protocol and a second interface circuit implementing a second data transfer protocol, the second data transfer protocol having a higher data transfer bandwidth than the first data transfer protocol, wherein the first memory controller receives over the first interface circuit transactions issued by a first host processor to be carried out by the first memory controller, and the first memory controller receives over the second interface circuit transactions issued by a second host processor to be carried out by the first memory controller, the first and second host processors storing data in the one or more three-dimensional memory arrays of the first plurality of memory circuits, the stored data to be accessed by the first host processor and the second host processor over respective first and second interface circuits” Whereas claim 1 of (U.S. PN: 11,301,172) “A memory module, comprising: a first semiconductor die, having formed thereon a first set of one or more quasi-volatile memory arrays (“QV memory arrays”) and a first group of interconnect conductors for sending and receiving data and control signals associated with reading, writing or erasing of the QV memory arrays; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die having formed thereon a memory controller circuit including an internal bus connecting the memory controller and the first set of QV memory arrays through the first group of interconnection conductors, and wherein the memory controller sends and receives the data and control signals to access the first set of QV memory arrays during reading, writing or erasing operations”.
The examiner would like to point out that claim 2 of the present application is substantially the same of claim 1 of (U.S. Patent No. 11,301,172). One is just an embodiment of the other and also the claims are obvious variations of each other and not patentably distinct.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Dependent claims of the instant application are deemed obvious over the dependent claims U.S. patent no. 11,301,172 for the same rationales discussed above.
Independent claim 11 of the instant application have corresponding issues with the independent claim 1 of (U.S. PN: 12,242,759), (U.S. PN: 11,954,363), and (U.S. PN: 11,301,172) Is also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Allowable Subject Matter
Claims 2-17 would be allowable if the applicant files Terminal Disclaimer to overcome the rejection(s) under obvious-type non-statutory double patenting, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamaki et al. (U.S. PN: 12,165,725) describe a memory system 1 includes one or more memory chips CP and one controller 200 as a NAND flash memory 100. Each of the memory chips CP is an example of a first memory. The controller 200 includes a host interface circuit (HOST UF) 201, a random-access memory (RAM) 202, a central processing unit (CPU) 203, a buffer memory 204, a NAND interface circuit (NAND UF) 205, and an error correction code circuit (ECC) 206. The host interface circuit 201 is connected to the host device 300 via a bus conforming to, for example, the serial advanced technology attachment (SATA) standards, the serial attached SCSI (SAS) standards, or the peripheral components interconnect (PCI) express (registered trademark) standards, and manages communication between the controller 200 and the host device 300.
Lee et al. (U.S. PN: 11,799,497) teach a storage controller 210 may include a host interface 211, a memory interface 212, and a processor 213. Also, the storage controller 210 may further include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218.
Kumano et al. (U.S. PN: 11,664,822) describe the memory system 1 may be a memory card or the like in which the memory controller 10 and the non-volatile memory 20 are configured as one package, or may be a solid state drive (SSD) or the like. The memory controller 10 controls writing to the non-volatile memory 20 according to a write request from the host 30. Further, the memory controller 10 controls reading from the non-volatile memory 20 according to a read request from the host 30. The memory controller 10 includes a host I/F (host interface) 15, a memory I/F (memory interface) 13, a control unit 11, an encoding/decoding unit (codec) 14, and a data buffer 12. The host I/F 15, the memory I/F 13, the control unit 11, the encoding/decoding unit 14, and the data buffer 12 are connected to each other by an internal bus 16.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights