CTNF 19/061,851 CTNF 74911 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are now pending in the application under prosecution and have been examined. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented. The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art. In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. 37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features. Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c). Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070050564 (GUNNA) in view of US 20200174697 (BRENNAN) . With respect to claim 1, GUNNA (US 20070050564 ) teaches method comprising: receiving, at a controller, signaling indicative of a write request, the write request including an address and data (control unit of an interface unit, the interface unit 24 to receive the request address and other request information, and corresponding request data for processor core write requests (Data Out)) [Par. 0027; Par. 0035]; determining, by a write request buffer of the controller, that the address of the write request is different from one or more stored write requests in the write request buffer (requests that have been written to the address buffer 26 are subsequently compared to from the address buffer 26 (and corresponding data written to the data buffer 28 is subsequently compared from the data buffer 28), i.e., compare of the request address for a core request to the address buffer entries in the address buffer 26 generate the comparison results) [Par. 0049-0052] ; and responsive to determining that the address of the write request is different, storing the write request in the write request buffer (compare address with respect to the requests from previous addresses compare results in a miss from the address buffer) the control unit 40 to allocate an address buffer entry from the free list 48, and may write the load request to the allocated address buffer entry, allocating an entry as a write index to the address buffer 26 to write the load request into the address buffer 26 (the load request is queued in the request buffer queue)) [Par. 0056] in the case of a miss, the control unit 40 may allocate a buffer entry from the free list 48, and may write the store into the allocated address buffer entry and the store data into the allocated data buffer entry using pointer to allocated entry as the write index in the address buffer 26 and the data buffer 28 (block 106) [Fig. 6; Par. 0065] ; or responsive to determining that the address of the write request is not different (request, presented to the address buffer 26 for comparison purposes, being cacheable load requests that hit in the data cache) [Par. 0057] , removing, invalidating, or overwriting information from the write request buffer and storing the write request in the write request buffer, the information being included among the one or more stored write requests and having a same address as the address of the write request (load requests may be added if a request to the cache block is in the address buffer 26 or if a preceding store request that updates the cache block is in the address buffer 26 is a request to update one or more bytes) [Par. 0057; Par. 0065] In the case of a cacheable cache hit (in a cache state that permits the store update), the store data may comprise the cache block of data, with the store data merged into the cache block; there is a match of the store address in the address buffer 26 (decision block 100, "yes" leg), and the match is on a buffer entry that is not being used for a store merge (decision block 114, "no" leg), the control unit 40 may assert replay for the store request (block 104). If the match is not on a buffer entry being used for a store merge, the match may be, e.g., on a load request, a snoop request, or a writeback request. A buffer entry being used for a store merge is referred to below as a merge buffer) [Par. 0065-0067]. GUNNA teaches processor core generating requests to be transmitted on an interconnect (i.e., a bus related transaction) such as read and write requests to satisfy load and store operations defining permissible operations that a caching agent may perform on a cache block and each coherent agent to respond with an indication of the state of the cache block addressed by the address for coherent response on the bus interconnect [Par. 0025; Par. 0005; Par. 0007] , but fails to specifically teach signaling indicative of a write request directed to a memory device. However, BRENNAN teaches operation combiner receives a series of commands with a modification operation and write addresses, wherein the operation combiner receives a first command including a first write address, the operation combiner compares the first write address to one or more second write address of a second command stored in a buffer, the operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison; the operation combiner stores collected commands having read or write addresses that do not match, e.g., incompatible commands [Abstract; Par. 0065-0066; Par. 0020; Par. 0011] . Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to combine the related transaction write with compare feature, as taught by GUNNA, with the command compared operations generated match or mismatch, as taught by BRENNAN, in order to define mask that is applied to the data in the address range associated with the new and matching commands to identify addresses that are operated on by the aggregate command, as taught by BRENNAN [Par. 0011] . The combination of GUNNA and BRENNAN is proper because BRENNAN teaches: “[0074] At block 730, the command is added to the buffer. The command that is added to the buffer is the received command if the read or write addresses in the received command did not match the read and write addresses in any buffered commands. The command that is added to the buffer is a combined or aggregated command if the read or write addresses in the received command match the read and write addresses in one of the buffered commands.” With respect to claim 15, GUNNA teaches apparatus comprising: a controller configured to: manage signaling indicative of write requests and read requests (integrated onto a single integrated circuit chip including a processor core and control unit, the control unit of an interface unit coupled to receive data out and manage data in to the core, the interface unit to receive the request address and other request information, and corresponding request data for processor core write requests (Data Out)) [Par. Par. 0022-0023; Par. 0027; Par. 0035] ; and receive signaling indicative of a write request, the write request including an address and data (the control unit receiving requests that have been written to the address buffer 26 are subsequently compared to from the address buffer 26 (and corresponding data written to the data buffer 28 is subsequently compared from the data buffer 28), i.e., compare of the request address for a core request to the address buffer entries in the address buffer 26 generate the comparison results) [Par. 0049-0052] ; and a write request buffer that is configured to: determine that the address of the write request is different from one or more stored write requests in the write request buffer and responsive to a determination that the address of the write request is different, store the write request in the write request buffer; (the address buffer used to compare address with respect to the requests from previous addresses compare results in a miss from the address buffer) the control unit 40 to allocate an address buffer entry from the free list 48, and may write the load request to the allocated address buffer entry, allocating an entry as a write index to the address buffer 26 to write the load request into the address buffer 26 (the load request is queued in the request buffer queue)) [Par. 0056] in the case of a miss (i.e., the compared address being different), the control unit 40 may allocate a buffer entry from the free list 48, and may write the store into the allocated address buffer entry and the store data into the allocated data buffer entry using the pointer to the allocated entry as the write index in the address buffer 26 and the data buffer 28 (block 106) [Fig. 6; Par. 0065] ; or responsive to a determination that the address of the write request is not different, remove, invalidate, or overwrite information from the write request buffer and store the write request in the write request buffer, the information being included among the one or more stored write requests and having a same address as the address of the write request (request, presented to the address buffer 26 for comparison purposes, being cacheable load requests that hit in the data cache) [Par. 0057] ; (load requests may be added if a request to the cache block is in the address buffer 26 or if a preceding store request that updates the cache block is in the address buffer 26 is a request to update one or more bytes) [Par. 0057; Par. 0065] In the case of a cacheable cache hit (in a cache state that permits the store update), the store data may comprise the cache block of data, with the store data merged into the cache block; there is a match of the store address in the address buffer 26 (decision block 100, "yes" leg), and the match is on a buffer entry that is not being used for a store merge (decision block 114, "no" leg), the control unit 40 may assert replay for the store request (block 104). If the match is not on a buffer entry being used for a store merge, the match may be, e.g., on a load request, a snoop request, or a writeback request. A buffer entry being used for a store merge is referred to below as a merge buffer) [Par. 0065-0067]. GUNNA teaches processor core generating requests to be transmitted on an interconnect (i.e., a bus related transaction) such as read and write requests to satisfy load and store operations defining permissible operations that a caching agent may perform on a cache block and each coherent agent to respond with an indication of the state of the cache block addressed by the address for coherent response on the bus interconnect [Par. 0025; Par. 0005; Par. 0007] , but fails to specifically teach signaling indicative of a write request directed to a memory device. However, BRENNAN teaches operation combiner receives a series of commands with a modification operation and write addresses, wherein the operation combiner receives a first command including a first write address, the operation combiner compares the first write address to one or more second write address of a second command stored in a buffer, the operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison; the operation combiner stores collected commands having read or write addresses that do not match, e.g., incompatible commands [Abstract; Par. 0065-0066; Par. 0020; Par. 0011] . Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to combine the related transaction write with compare feature, as taught by GUNNA, with the command compared operations generated match or mismatch, as taught by BRENNAN , in order to define mask that is applied to the data in the address range associated with the new and matching commands to identify addresses that are operated on by the aggregate command, as taught by BRENNAN [Par. 0011] . With respect to claim 17, GUNNA teaches apparatus comprising: at least one memory array; a controller coupled to the at least one memory array (main memory system integrated onto a single integrated circuit chip including a processor core and control unit, the control unit to manage memory in the main memory system wherein the memory in the main memory system may comprise any desired type of memory) [Fig. 1; Par. 0033; Par. 0022-0023] , the controller configured to: manage signaling indicative of write requests and read requests (the control unit of an interface unit coupled to receive data out and provide data in to the core, the interface unit to receive the request address and other request information, and corresponding request data for processor core write requests (Data Out)) [Par. Par. 0022-0023; Par. 0027; Par. 0035] ; and receive signaling indicative of a write request, the write request including an address and data (the controller to receive requests that have been written to the address buffer 26 are subsequently compared to from the address buffer 26 (and corresponding data written to the data buffer 28 is subsequently compared from the data buffer 28), i.e., compare of the request address for a core request to the address buffer entries in the address buffer 26 generate the comparison results) [Par. 0049-0052]; and a write request buffer that is configured to: determine that the address of the write request is different from one or more stored write requests in the write request buffer and responsive to a determination that the address of the write request is different, store the write request in the write request buffer (the address buffer used to compare address with respect to the requests from previous addresses, the compare resulting in a miss from the address buffer) the control unit 40 to allocate an address buffer entry from the free list 48, and may write the load request to the allocated address buffer entry, allocating an entry as a write index to the address buffer 26 to write the load request into the address buffer 26 (the load request is queued in the request buffer queue)) [Par. 0056] in the case of a miss (i.e., the compared address being different), the control unit 40 may allocate a buffer entry from the free list 48, and may write the store into the allocated address buffer entry and the store data into the allocated data buffer entry using the pointer to the allocated entry as the write index in the address buffer 26 and the data buffer 28 (block 106) [Fig. 6; Par. 0065] ;; or responsive to a determination that the address of the write request is not different, remove, invalidate, or overwrite information from the write request buffer and store the write request in the write request buffer, the information being included among the one or more stored write requests and having a same address as the address of the write request. (request, presented to the address buffer 26 for comparison purposes, being cacheable load requests that hit in the data cache) [Par. 0057] ; (load requests may be added if a request to the cache block is in the address buffer 26 or if a preceding store request that updates the cache block is in the address buffer 26 is a request to update one or more bytes) [Par. 0057; Par. 0065] In the case of a cacheable cache hit (in a cache state that permits the store update), the store data may comprise the cache block of data, with the store data merged into the cache block; there is a match of the store address in the address buffer 26 (decision block 100, "yes" leg), and the match is on a buffer entry that is not being used for a store merge (decision block 114, "no" leg), the control unit 40 may assert replay for the store request (block 104). If the match is not on a buffer entry being used for a store merge, the match may be, e.g., on a load request, a snoop request, or a writeback request. A buffer entry being used for a store merge is referred to below as a merge buffer) [Par. 0065-0067]. GUNNA teaches processor core generating requests to be transmitted on an interconnect (i.e., a bus related transaction) such as read and write requests to satisfy load and store operations defining permissible operations that a caching agent may perform on a cache block and each coherent agent to respond with an indication of the state of the cache block addressed by the address for coherent response on the bus interconnect [Par. 0025; Par. 0005; Par. 0007] , but fails to specifically teach signaling indicative of write requests and read requests directed to the at least one memory array. However, BRENNAN teaches operation combiner receives a series of commands with a modification operation and read addresses and write addresses, wherein the operation combiner receives a first command including receive a first command including one or more first read addresses and a first write address, operation combiner comparing the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer, the operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison; the operation combiner stores collected commands having read or write addresses that do not match, e.g., incompatible commands [Abstract; Par. 0065-0066; Par. 0020; Par. 0011] . Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to combine the related transaction write with compare feature, as taught by GUNNA, with the command compared operations generated match or mismatch, as taught by BRENNAN , in order to define mask that is applied to the data in the address range associated with the new and matching commands to identify addresses that are operated on by the aggregate command, as taught by BRENNAN [Par. 0011] . With respect to claim 2, GUNNA and BRENNAN, combined teach the method, wherein determining that the address of the write request is different comprises: comparing, by the write request buffer, the address of the write request with stored addresses, the stored addresses corresponding to addresses received in the one or more stored write requests of the write request buffer ( the address buffer is used to compare address with respect to the requests from previous addresses from the address buffer [GUNNA’s Par. 0056; Par. 0065] The combiner determines whether the read and write addresses in the received command match the read and write addresses in the buffered command, the command including read addresses in the command, for the combiner compare the addresses in the received and buffered commands) [BRENNAN’s Par. 0070-0071]. With respect to claim 3, GUNNA and BRENNAN, combined teach the method, wherein the stored addresses are stored in a dedicated portion of the write request buffer ( requests retained in request queue such that the requests may be dynamically allocated into any free entry in the buffers 26 and 28 as they arrive and the queues 44A-44C may retain the order of requests) [GUNNA’s Par. 0037]. With respect to claim 4, GUNNA and BRENNAN, combined teach the method, wherein the dedicated portion of the write request buffer is configured to store a single entry for each address of a plurality of addresses associated with the memory device (for address of the command that match, combining the received and buffered commands includes merging masks associated with the received and buffered commands, i.e., command added to the buffer being a combined or aggregated command if the read or write addresses in the received command match the read and write addresses in one of the buffered commands) [BRENNAN’s Par. 0072; Par. 0074] . With respect to claim 5, GUNNA and BRENNAN, combined teach the method, further comprising: storing the write request at an initial position of the write request buffer in response to determining that the address of the write request is different ( requests retained in request queue such that the requests may be dynamically allocated into any free entry in the buffers 26 and 28 as they arrive and the queues 44A-44C may retain the order of requests) [GUNNA’s Par. 0037] With respect to claim 6, GUNNA and BRENNAN, combined teach the method, further comprising: determining that the write request buffer comprises a quantity of information that is greater than a threshold; and removing, invalidating, or overwriting, in response to storing the write request and the write request buffer comprising the quantity of information that is greater than the threshold, an address and data associated with an oldest write request from the write request buffer (requests being dynamically allocated into any free entry in the buffers 26 and 28 as they arrive, total number of requests may not exceed the total number of entries, when a buffer entry is allocated to a request, wherein, a credit is consumed (i.e., the request processed) the buffer entry is freed via completion of a request as the queues 44A-44C retaining the order of requests (operated as a first-in, first-out (FIFO)) [GUNNA’s Par. 0038-0039] . With respect to claim 7, GUNNA and BRENNAN, combined teach the method, further comprising: storing the write request at an initial position of the write request buffer in response to determining that the address of the write request is not different (requests being dynamically allocated into any free entry in the buffers 26 and 28 as they arrive with additional cacheable stores to the same cache block may be merged into the address buffer entry/data buffer entry resulting in a single transaction to reduce bandwidth) [GUNNA’s Par. 0030; Par. 0036-0039]; (command added to the buffer being a combined or aggregated command if the read or write addresses in the received command match the read and write addresses in one of the buffered commands) [BRENNAN’s Par. 0072; Par. 0074] . With respect to claim 8, GUNNA and BRENNAN, combined teach the method, further comprising: removing an address and data associated with the information from the write request buffer in response to storing the write request (data buffer to write the data into the identified data buffer entry, supplying the cache block for a load miss triggering a writeback of evicted cache block, reusing the entry storing the load miss cache block for the write back request, wherein: the requests being dynamically allocated into any free entry in the buffers 26 and 28 as they arrive, total number of requests may not exceed the total number of entries, a credit is consumed (i.e., the request processed) the buffer entry is freed via completion of a request as the queues 44A-44C retaining the order of requests) [GUNNA’s Par. 0038-0039 Par. 0062-0063] . With respect to claim 9, GUNNA and BRENNAN, combined teach the method, further comprising: storing the address of the write request in a write address buffer of the write request buffer; and storing the data of the write request in a write data buffer of the write request buffer (interface unit 24 includes an address buffer 26 and data buffer 28, the address buffer 26 configured to store addresses of requests and the data buffer 28 configured to store data corresponding to the request) [GUNNA’s Par. 0029-0030] . With respect to claim 10, GUNNA and BRENNAN, combined teach the method, wherein a position of the write request in the write request buffer represents an order in which the write request was stored (requests being dynamically allocated into any free entry in the buffers 26 and 28 as they arrive maintaining or order and the order maintained) Par. 0036-0039] . With respect to claim 11, GUNNA and BRENNAN, combined teach the method, further comprising: storing the address and the data of the write request in response to the controller transmitting the write request to the memory device (in addition to writing the cache block to the data cache, the interface unit to provide address information to permit forwarding of data to loads that are awaiting the cache block) [GUNNA’s Par. 0063] . With respect to claim 12, GUNNA and BRENNAN, combined teach the method, wherein a buffer depth of the write request buffer is determined based on a reuse distance metric, the reuse distance metric representing an average number of unique write request entries stored in the write request buffer between an incoming read request that has a same address as an address of a write request stored in the write request buffer (number of each type of buffer carefully selected to provide the desired level of performance with entries in the address buffer 26 and data buffer 28 dynamically allocated to requests as needed in the case that a relatively large number of the same type of request occur in a short period of time; total number of requests may not exceed the total number of entries, when a buffer entry is allocated to a request, wherein, a credit is consumed (i.e., the request processed) the buffer entry is freed via completion of a request as the queues 44A-44C retaining the order of requests) [GUNNA’s Par. 0038-0039; Par. 0029-0030). With respect to claim 16, GUNNA and BRENNAN, combined teach apparatus, further comprising: an initiator configured to initiate memory requests, wherein: the controller comprises a link controller; the initiator comprises the link controller; and the link controller comprises the write request buffer (processor or I/O interfaces initiating requests or commands, interface control unit coupled to interconnect receive transactions from the I/O devices or interfaces and to generate corresponding transactions on the interconnect that performed as a cache coherent transaction) {GUNNA’s Par. 0028; Par. 0032] . With respect to claim 18, GUNNA and BRENNAN, combined teach the apparatus, wherein the write request buffer is configured to: store an address and data associated with a most-recent write request at an initial position of the write request buffer (requests being dynamically allocated and stored into any free entry in the buffers 26 and 28 as they arrive, total number of requests may not exceed the total number of entries, when a buffer entry is allocated to a request, wherein the request processed as the buffer entry is freed retaining the order of requests) [GUNNA’s Par. 0038-0039] . With respect to claim 19, GUNNA and BRENNAN, combined teach the apparatus, further comprising: one or more memory controllers, wherein: the write request buffer is coupled between the controller and the one or more memory controllers; and the one or more memory controllers are coupled between the write request buffer and the at least one memory array (integrated system onto a single integrated circuit chip including control unit, the control unit to manage memory in the main memory system wherein the memory in the main memory system may comprise any desired type of memory, the control unit coupled to receive data out and provide data in to the core, the interface unit to receive the request address and other request information, and corresponding request data for processor core write requests) [Fig. 1; Par. 0022-0023; Par. 0027; Par. 0033-0035] . With respect to claim 20, GUNNA and BRENNAN, combined teach the apparatus, wherein: the controller is configured to: receive signaling indicative of a read request, the read request including an address; and the write request buffer is configured to: determine if the address of the read request matches an address associated with a write request of the one or more stored write requests in the write request buffer; and responsive to a determination that the address of the read request matches an address associated with a write request of the one or more stored write requests, add the read request to a response queue associated with the write request buffer; or responsive to a determination that the address of the read request does not match an address associated with a write request of the one or more stored write requests, transmit the read request to the one or more memory controllers (control unit is configured for read and write the address buffer to read or write the first address buffer entry, and wherein the control unit is configured to read as an index to the address buffer to read or write the second address buffer entry) [GUNNA’s Par. 0029-0032]; combiner receive a first command including one or more first read addresses and a first write address, the operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer [Abstract] as new command arrives at the front end, the new command is compared to commands that were previously received at the front end and stored in the buffer; If the new command matches one of the previously received commands, the new command and the matching previous command are combined into an aggregate command that is stored in the buffer for eventual dispatch to a back end of the pipeline, i.e, comparing write addresses or read addresses of the new and matching commands, as well as determining whether the write and read addresses are within the same address range [Par. 0011]; when a match occurs if the read and write addresses indicate the same cache line, e.g., the read and write addresses in the received command and the buffered command are the same, the op combiner 240 combines the received command with the buffered command in response to a match between the read and write addresses) BRENNER’s Par. 0020; Par. 0036-0037] . BRENNER teaches the command that is added to the buffer is the received command if the read or write addresses in the received command did not match the read and write addresses in any buffered commands. The command that is added to the buffer is a combined or aggregated command if the read or write addresses in the received command match the read and write addresses in one of the buffered commands . 07-21-aia AIA Claim s 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070050564 (GUNNA) in view of US 20200174697 (BRENNAN) and further in view of US 20220358042 A1 (MALLADI et al) . With respect to claim 13, GUNNA teaches processors generating requests and controller receiving coherency related store requests for requests from interconnect, the store request satisfying store operations defining permissible operations that a caching agent may perform on a cache block and each coherent agent to respond with an indication of the state of the cache block addressed by the address for coherent response on the bus interconnect [Par. 0023-0025] . Neither GUNNA nor BRENNAN specifically teaches controller comprises a Compute Express Link (CXL) controller. However, memory device including features for handling the ordering of read and write operations, such memory device to address the challenge that remote Compute Express Link (CXL) controller system manages internal ordering for subsequent read operations and write operation [Fig 2C; Par. 0054]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to use the Compute Express Link (CXL) controller within the combined command dependency comparison taught by GUNNA and BRENNAN , in order to handle the ordering of read and write operations maintaining a time stamp, an address, and any dependencies for transactions (coherency), as taught by MALLADI [Par. 000054] With respect to claim 14, GUNNA, BRENNAN and MALLADI, combined teach the memory device comprises a Type 1 CXL device, a Type 2 CXL device, or a Type 3 CXL device [MALLADI’s Par. 0044-0047] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20030074530 A1 (MAHALINGAIAH et al) teaching load/store unit comprising a load/store buffer and a memory access buffer. The load store buffer is coupled to a data cache and is configured to store information on memory operations. The memory access buffer is configured to store addresses and data associated with the requested addresses for at least one of the most recent memory operations. The memory access buffer, upon detecting a load memory operation, outputs data associated with the load memory operation's requested address. If the requested address is not stored within the memory access buffer, the memory access buffer is configured to store the load memory operation's requested address and associated data when it becomes available from the data cache. Similarly, store memory operation requested address and associated data is also stored. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138 Application/Control Number: 19/061,851 Page 2 Art Unit: 2138 Application/Control Number: 19/061,851 Page 3 Art Unit: 2138 Application/Control Number: 19/061,851 Page 4 Art Unit: 2138 Application/Control Number: 19/061,851 Page 5 Art Unit: 2138 Application/Control Number: 19/061,851 Page 6 Art Unit: 2138 Application/Control Number: 19/061,851 Page 7 Art Unit: 2138 Application/Control Number: 19/061,851 Page 8 Art Unit: 2138 Application/Control Number: 19/061,851 Page 9 Art Unit: 2138 Application/Control Number: 19/061,851 Page 10 Art Unit: 2138 Application/Control Number: 19/061,851 Page 11 Art Unit: 2138 Application/Control Number: 19/061,851 Page 12 Art Unit: 2138 Application/Control Number: 19/061,851 Page 13 Art Unit: 2138 Application/Control Number: 19/061,851 Page 14 Art Unit: 2138 Application/Control Number: 19/061,851 Page 15 Art Unit: 2138 Application/Control Number: 19/061,851 Page 16 Art Unit: 2138 Application/Control Number: 19/061,851 Page 17 Art Unit: 2138 Application/Control Number: 19/061,851 Page 18 Art Unit: 2138 Application/Control Number: 19/061,851 Page 19 Art Unit: 2138 Application/Control Number: 19/061,851 Page 20 Art Unit: 2138 Application/Control Number: 19/061,851 Page 21 Art Unit: 2138 Application/Control Number: 19/061,851 Page 22 Art Unit: 2138 Application/Control Number: 19/061,851 Page 23 Art Unit: 2138
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