DETAILED ACTION
This action is in response to the Application filed on 02/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --CONTROL CIRCUIT WITH OVER-CURRENT PROTECTION AND POWER SUPPLY CIRCUIT--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1 – 2, 6 – 7, 11 – 12 and 16 – 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2013/0083442; (hereinafter Hiyama), cited by Applicant(s) in view of US Pub. No. 2011/0279930; (hereinafter Lin).
Regarding claim 1, Hiyama [e.g. Fig. 2] discloses a control circuit for a power semiconductor [e.g. 1] which operates depending on a control signal [e.g. output of 2] applied to a control terminal [e.g. gate terminal], comprising: a detection value comparison unit [e.g. 32] which compares a current detection value [e.g. output of 4 and 5] depending on a main current flowing through the power semiconductor [e.g. paragraph 029 recites “The sense resistor 4 is connected to between the sense terminal and an emitter terminal of the IGBT 11, and is a passive element that converts a sense current to a voltage (sense voltage)”] and a set current threshold [e.g. output of 34 being input to inverting input of 32; paragraph 037 recites “an output of the comparator 32 is on an L (Low) level when a sense voltage inputted into the positive terminal is lower than the voltage of the negative terminal (first reference voltage VREF1 or the second reference voltage VREF2), and the output is on an H (High) level when the sense voltage exceeds a voltage of the negative terminal”]; and a protection control unit [e.g. 33] which controls at least any one of the current threshold [e.g. VREF1 / VREF2; paragraph 035 recites “Switching as to whether the negative terminal of the comparator 32 is connected with the reference voltage source 37 or with the voltage division reference point 38 is performed by the switch 34, and its operation is controlled by the delay circuit 33”], the duration, or an extraction rate of electric charges from the control terminal based on a control power supply voltage which determines an amplitude of the control signal.
Even though the claim does not require that the protection control unit controls the current threshold based on a control power supply voltage which determines an amplitude of the control signal, Hiyama further discloses that unit 33 controls the threshold voltage between VREF1 and VREF2 based on VIN which is a control power supply voltage which determined an amplitude of the control signal [e.g. paragraphs 031 – 032 recite “The driving circuit 2 generates a driving signal to be inputted into a gate of the IGBT 11 based on an input signal VIN as a control signal to be inputted from the outside. It is assumed herein that the switching element 1 is controlled so as to be turned on with the input signal VIN being on an H level, and turned off with the input signal VIN being on an L level. The input signal VIN is supplied to the driving circuit 2 through the overcurrent protection circuit 3. The overcurrent protection circuit 3 monitors a main current flowing through the switching element 1 based on the sense voltage, and normally transmits the input signal VIN to the driving circuit 2. However, when detecting that an overcurrent has flowed through the switching element 1 (the main current has exceeded the SC trip level), the overcurrent protection circuit 3 halts the supply of the input signal VIN to the driving circuit 2, to perform a predetermined protection operation such as cutting off of the switching element 1.” Paragraph 035 recites “The delay circuit 33 controls the switch 34, to connect the reference voltage source 37 to the negative terminal of the comparator 32 only during a period from rising of the input signal VIN until lapse of predetermined delay time thereafter, and connect the voltage division reference point 38 to the negative terminal of the comparator 32 during the other periods”].
Hiyama fails to disclose a protection unit which, when a state in which the current detection value exceeds the current threshold has lasted longer than a set duration, suppresses the main current flowing through the power semiconductor.
Lin [e.g. Figs. 1 – 2, 4] teaches a protection unit [e.g. Fig. 2; 22 - 23] which, when a state in which the current detection value exceeds the current threshold [e.g. Fig. 2; determined by 21] has lasted longer than a set duration, suppresses the main current [e.g. Fig. 1; IL] flowing through the power semiconductor [e.g. 13; paragraph 026 recites “The over current judgment circuit 21 compares the current sense signal CS with a current limit CL to determine whether an over current condition occurs, and the over current judgment circuit 21 generates an over current indication signal OC which is inputted to both a time comparison circuit 22 and a timer 23… The timer 23 receives the over current indication signal OC and counts the pulse number of the over current indication signal OC, that is, the timer 23 counts the lasting time of the over current condition. When this over current condition lasts longer than the first time period T1, the switching regulator control circuit 20 outputs an output short-circuit protection signal to trigger an output short-circuit protection measure.” Paragraph 027 recites “the time comparison circuit 22 compares the clock signal CLK and the over current indication signal OC to determine whether an over current condition is caused by output short-circuit. The time comparison circuit 22 outputs an output short-circuit indication signal OSH to the timer 23. If the output short-circuit indication signal OSH indicates an output short-circuit condition, the timer 23 changes to the second time setting, wherein it counts the pulse number of the over current indication signal OC to determine whether the over current condition lasts longer than the second time period T2 which is shorter. And if yes, the switching regulator control circuit 20 outputs an output short-circuit protection signal to trigger an output short-circuit protection measure.” See Fig. 4 with respect to OSH after second pulse of clock to activate the short circuit protection signal which turns OFF the transistor switch 13].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hiyama by a protection unit which, when a state in which the current detection value exceeds the current threshold has lasted longer than a set duration, suppresses the main current flowing through the power semiconductor as taught by Lin in order of being able to avoid triggering false over current protection condition.
Regarding claim 2, Hiyama [e.g. Fig. 2] discloses wherein the protection control unit controls the current threshold [e.g. VREF1 / VREF2; paragraph 035 recites “Switching as to whether the negative terminal of the comparator 32 is connected with the reference voltage source 37 or with the voltage division reference point 38 is performed by the switch 34, and its operation is controlled by the delay circuit 33”].
Regarding claim 6, Hiyama fails to disclose wherein the protection control unit controls the duration. However, preceding claim 1 requires the protection control unit controls at least any one of the current threshold, the duration, or an extraction rate of electric charges from the control terminal based on a control power supply voltage which determines an amplitude of the control signal.
Regarding claim 7, Hiyama fails to disclose wherein the protection control unit controls the extraction rate. However, preceding claim 1 requires the protection control unit controls at least any one of the current threshold, the duration, or an extraction rate of electric charges from the control terminal based on a control power supply voltage which determines an amplitude of the control signal.
Regarding claims 11 – 12 and 16 – 17, Hiyama [e.g. Fig. 2] discloses A power supply circuit [e.g. paragraph 04 suggest that the control circuit and the power semiconductor are applied to an inverter power supply; paragraph 04 recites “As a semiconductor device provided with a semiconductor switching element (hereinafter simply referred to as "switching element"), such as an inverter, there is a semiconductor device having an overcurrent protection circuit which performs a protection operation, such as cutting off of the switching element, to protect the switching element when a main current flowing through the switching element exceeds a certain level”] comprising: the control circuit according to claims 1 – 2 and 6 - 7, respectively; and the power semiconductor.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiyama in view of Lin and further in view of US Pub. No. 2017/0373583; (hereinafter Nakajima).
Regarding claim 8, Hiyama fails to disclose further comprising an extraction transistor which controls whether the control terminal is connected to a reference potential, wherein the protection control unit controls at least one of a channel area of the extraction transistor or a gate voltage applied to the extraction transistor.
Nakajima [e.g. Fig. 1] teaches further comprising an extraction transistor [e.g. 35] which controls whether the control terminal [e.g. gate of 21m] is connected to a reference potential [e.g. ground by turning ON and OFF the transistor 35], wherein the protection control unit [e.g. 37, 38] controls at least one of a channel area of the extraction transistor or a gate voltage applied to the extraction transistor [e.g. output of 28 to gate of 35 for turning it ON and OFF].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hiyama by further comprising an extraction transistor which controls whether the control terminal is connected to a reference potential, wherein the protection control unit controls at least one of a channel area of the extraction transistor or a gate voltage applied to the extraction transistor as taught by Nakajima in order of being able to provide current limit operation so as to maintain the current under limit values.
Regarding claims 18, Hiyama [e.g. Fig. 2] discloses A power supply circuit [e.g. paragraph 04 suggest that the control circuit and the power semiconductor are applied to an inverter power supply; paragraph 04 recites “As a semiconductor device provided with a semiconductor switching element (hereinafter simply referred to as "switching element"), such as an inverter, there is a semiconductor device having an overcurrent protection circuit which performs a protection operation, such as cutting off of the switching element, to protect the switching element when a main current flowing through the switching element exceeds a certain level”] comprising: the control circuit according to claims 8; and the power semiconductor.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiyama in view of Lin and further in view of US Pub. No. 2006/0077000; (hereinafter Guodo).
Regarding claim 9, Hiyama fails to disclose further comprising: a discharge resistor provided on a path for discharging the control terminal, wherein the protection control unit controls a resistance value of the discharge resistor.
Guodo [e.g. Fig. 1] teaches further comprising: a discharge resistor [e.g. 4,5] provided on a path for discharging the control terminal [e.g. gate of 1], wherein the protection control unit [e.g. 7; paragraph 042 recites “The operation of the semiconductor device is divided into two operations: one in a period during which the timer circuit 7 outputs an L-level signal which hereinafter will be called "a normal operation", and the other one in a period during which the timer circuit 7 outputs an H-level signal which hereinafter will be called "a protecting operation”] controls a resistance value of the discharge resistor [e.g. by operating ON/OFF of transistor 11; paragraph 045 recites “The timer circuit 7 outputs an L-level signal. The output of the timer circuit 7 is reversed at the inverter 8 to be input to the gate of the NMOS transistor 11 as an H-level signal. Since the NMOS transistor 11 is brought into the ON state, current flowing in the gate discharge resistor part 101 flows out from the resistor 4 to a ground potential through the NMOS transistor 11. Therefore, the resistance of the gate discharge resistor part 101 becomes almost equal to that of the resistor 4.” Paragraph 051 recites “The signal output from the timer circuit 7 is reversed at the inverter 8, and is input to the gate of the NMOS transistor 11 as an L-level signal. Upon receipt of the L-level signal, the NMOS transistor 11 is turned into the OFF state from the ON state. Accordingly, the resistance of the gate discharge resistor part 101 is equal to a combined resistance of the resistors 4 and 5”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Hiyama by further comprising: a discharge resistor provided on a path for discharging the control terminal, wherein the protection control unit controls a resistance value of the discharge resistor as taught by Guodo in order of being able to forcedly stopping the switching device for the sake of protecting against damage.
Regarding claims 19, Hiyama [e.g. Fig. 2] discloses A power supply circuit [e.g. paragraph 04 suggest that the control circuit and the power semiconductor are applied to an inverter power supply; paragraph 04 recites “As a semiconductor device provided with a semiconductor switching element (hereinafter simply referred to as "switching element"), such as an inverter, there is a semiconductor device having an overcurrent protection circuit which performs a protection operation, such as cutting off of the switching element, to protect the switching element when a main current flowing through the switching element exceeds a certain level”] comprising: the control circuit according to claims 9; and the power semiconductor.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 3 – 5, 10, 13 – 15 and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the protection unit comprises: a first protection device which, when the state in which the current detection value exceeds the current threshold has lasted longer than the set duration, suppresses the main current flowing through the power semiconductor; and a second protection device which, when the state in which the current detection value exceeds the current threshold has lasted longer than the set duration and the control power supply voltage exceeds a set voltage threshold, further suppresses the main current flowing through the power semiconductor”.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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