Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (2022/0254305) hereinafter, Yeh in view of Jeon et al (2010/0225637) hereinafter, Jeon.
In regards to claim 1, Yeh teaches an electronic device, comprising (abstract):
A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.(Abstract)
a first electronic panel (fig. 1 (103)), comprising a plurality of signal lines, wherein the plurality of signal lines are divided into a plurality of signal line groups (fig. 1 OUTR, OURG and OUTB);
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a plurality of first signal drivers (fig. 1 (101s)), electrically connected to the plurality of signal line groups respectively, wherein two adjacent ones of the plurality of first signal drivers are electrically connected to each other (fig. 1 connection carrying data between 101s)); and
[0019] FIG. 1 is a schematic diagram of a LED driving apparatus 100 according to an embodiment of the disclosure. The LED driving apparatus 100 includes a plurality of LED drivers 101, a controller 102, and a plurality of LEDs 103. The plurality of LED drivers 101 include cascaded N stages LED drivers from LED driver 1 to LED driver N, and N is a positive number. The controller 102 outputs an original data signal to the first stage LED driver 1, the first stage LED driver 1 receives the original data signal and outputs a first data signal data_1 to the second stage LED driver 2, and the (N−1)th stage LED driver (N−1) receives a (N−2)th data signal data_(N−2) and outputs the (N−1)th data signal data_(N−1) to the Nth stage LED driver N.
a controller (fig. 1 (102)), electrically connected to a first-level signal driver in the plurality of first signal drivers (fig. 1 101 and 102 [0019-0022]), and
configured to transmit a clock embedded digital signal to the first-level signal driver, [006-0010,0020-0025,0031]
[0006] A LED driving apparatus with clock embedded cascaded LED drivers that are capable of performing data transmission without the common clock signal line and therefore avoiding the limitation of the speed of the data transmission due to the large parasitic capacitance from the common clock signal line and the skew between the common clock signal and the data signal in each of the cascaded LED drivers is introduced.
wherein the plurality of first signal drivers use to sequentially transmit the clock embedded digital signal from the first-level signal driver to an N.sup.th-level signal driver in the plurality of first signal drivers in a cascade manner, wherein N is greater than 1 (fig. 1 and fig. 4 (101s, SDIN SDOUT, etc) [0020-0031].
Yeh fails to expressly teach point-to-point connection.
However, Jeon teaches point-to-point connection (fig. 1 (200)[0017]).
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Yeh to further include point-to-point connection as taught by Jeon in order to help reduce impedance mismatches.
In regards to claim 2, Yeh and Jeon to teach the electronic device as claimed in claim 1, wherein the clock embedded digital signal is a differential signal.[0024] Jeon.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh and Jeon in view of Kwon et al (2021/0241700) hereinafter, Kwon.
In regards to claim 3, Yeh and Jeon fail to expressly teach the electronic device as claimed in claim 1, wherein the first electronic panel further comprises: a gate driver, wherein the controller further transmits a gate control signal to the gate driver. Examiner notes scan lines of fig. 1.
However, Kwon teaches wherein the first electronic panel further comprises: a gate driver, wherein the controller further transmits a gate control signal to the gate driver. (fig. 1 (130) and GL1).
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Yeh and Jeon to further include wherein the first electronic panel further comprises: a gate driver, wherein the controller further transmits a gate control signal to the gate driver as taught by Kwon in order to apply the scan signal which applies the data to the pixel.
In regards to claim 4, Yeh and Jeon in view of Kwon teaches the electronic device as claimed in claim 3, wherein the controller is disposed on a circuit board, and the controller is electrically connected to the gate driver and the first-level signal driver through a flat cable structure and traces on the circuit board [0031] Yeh in view of (fig. 2 and 3 (110) (205/210) Kwon).
In regards to claim 5, Yeh and Jeon in view of Kwon, see rational of claim 3, teaches the electronic device as claimed in claim 1, wherein the controller is disposed on a circuit board, the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the circuit board. [0031] Yeh in view of (fig. 2 and 3 (110) (205/210) OC7/TD7 [0047] Kwon).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh and Jeon in view of Chen et al (2018/0336828) hereinafter, Chen.
In regards to claim 7, Yeh and Jeon fails to teach the electronic device as claimed in claim 1, wherein the controller is disposed on a circuit board, the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.
However, Chen teaches wherein the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.(fig. 2a and 2b 23)[0010, 0048] Chen
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It would have been obvious to been obvious to one of ordinary skill in the art to modify the teachings of Yeh and Jeon to further include wherein the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel reduce cost and increase the life span [0048]
Therefore, Yeh and Jeon in view of Chen teaches wherein the controller is disposed on a circuit board, the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.(fig. 1 (102, 101s traces) [0031-0035] Yeh in view .(fig. 2a and 2b 23)[0010, 0048] Chen
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh and Jeon in view of Chen et al (20060202938) hereinafter, Chen2.
In regards 8, Yeh fails to teach the electronic device as claimed in claim 1, wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through a flat cable structure and traces on the circuit board.
However, Chen2 teaches wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through a flat cable structure and traces on the circuit board [007-008] (fig. 1 120 and controller and (130 to 112s)).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Yeh and Jeon to further include wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through a flat cable structure and traces on the circuit board as taught by Chen2 in order to simplify manufacturing [0007].
In regards to claim 9, Yeh and Jeon fails to teach the electronic device as claimed in claim 1, wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.
However, Chen2 teaches wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.[009-0017] (fig. 2a (225 232 and C2/D2 and S/D).
It would have been obvious to one of ordinary skill in the art to modify the teachings of Yeh and Jeon to further include wherein the plurality of first signal drivers are disposed on the first electronic panel, the controller is disposed on a circuit board, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel as taught by Chen2 in order to decrease the possibility of electrical contact failure.[0008].
Allowable Subject Matter
Claims 6 and 10-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622