Detailed office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,2, 8 – 11, 17, 20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hormati (US Patent Number 11,303,484).
Regarding claims 1, and 17, Hormati discloses an apparatus and method (fig. 3) comprising: a sampler circuit (340, fig. 3; col 12, line 35) configured to: convert, in response to receiving a first code, the first code into a reference signal (col. 12, lines 45 – 47) and produce, in response to comparing an input signal to the reference signal, a bitstream (col. 12, lines 35 – 37); and a tracking filter (gates 342, 346, pattern counters 383, 384 and controller 350 form the tracking filter) configured to: update, upon receiving the bitstream from the sampler circuit, the first code using information contained in the bitstream, and output, in response to updating the first code, the first code to the sampler circuit (col. 12, line 48 to col. 13, line 1).
Regarding claim 20, Hormati discloses a device (fig. 3) comprising: a sampler circuit (340, fig. 3; col 12, line 35) configured to: convert a first code into a reference signal in response to receiving the first code (col. 12, lines 45 – 47), and produce a bitstream in response to comparing an input signal to the reference signal (col. 12, lines 35 – 37); a tracking filter (gates 342, 346, pattern counters 383, 384 and controller 350 form the tracking filter)configured to: update, upon receiving the bitstream from the sampler circuit, the first code using information contained in the bitstream, and output, in response to updating the first code, the first code to the sampler circuit (col. 12, line 48 to col. 13, line 1); and a register configured to: receive, from an electronic load, parameters for the tracking filter (paragraphs between col. 9 and 10; paragraph bridging col. 12 and 13).
Regarding claim 2, Hormati discloses an apparatus (fig. 3) wherein the first code is a DAC code (the DAC in fig. 3 receives a control signal).
Regarding claim 8, Hormati discloses an apparatus (fig. 3), wherein the first code represents discrete amplitude value of a valley envelope for the input signal (the DAC in fig. 3 receives a control signal).
Regarding claim 9, Hormati discloses an apparatus (fig. 3) wherein the reference signal is an analog signal (the DAC produces an analog signal).
Regarding claim 10, Hormati discloses an apparatus (fig. 3), wherein the first code comprises a fixed number of bits (abstract; “adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements” implies bit streams; also col. 4, lines 30 – 39 “Similarly, a vector signaling code receiver may directly detect the combination of received wire signals corresponding to a particular subchannel, as one example by using a multi-input comparator (MIC) performing a weighted summation of two or more wire signals correlated with the orthogonal mode of that subchannel, and directly producing one bit of received data”) .
Regarding claim 11, Hormati discloses an apparatus (fig. 3), wherein the bitstream is a stream of binary values (abstract; “adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements” implies bit streams; also col. 4, lines 30 – 39 “Similarly, a vector signaling code receiver may directly detect the combination of received wire signals corresponding to a particular subchannel, as one example by using a multi-input comparator (MIC) performing a weighted summation of two or more wire signals correlated with the orthogonal mode of that subchannel, and directly producing one bit of received data”) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 – 5, 7, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hormati (US Patent Number 11,303,484) in view of Fu Kuan-Lin et al. (a 64-Gb/s PAM-4 Optical receiver with amplitude Phase Correction and Threshold Voltage/Data Level Calibration) (Applicant Admitted Prior Art).
Regarding claims 3 – 5, 7, 12, Hormati discloses all the limitations discussed above except the apparatus further comprising: a calculator configured to calculate, in response to the tracking filter updating the first code, a value for a second code and a value for a third code (claim 3); the apparatus, wherein the second code is a correction code (claim 4); the apparatus wherein the third code is a gain code (claim 5); the apparatus, wherein the first code represents discrete amplitude value of a peak envelope for the input signal (Claim 7); the apparatus, wherein the tracking filter is configured to extract, in response to converting the bitstream into the first code, information from the bitstream indicating whether the input signal exceeds or falls below the reference signal (claim 12)
. However, Fu Kuan-Lin et al. disclose an apparatus further comprising: a calculator configured to calculate, in response to the tracking filter updating the first code, a value for a second code and a value for a third code (Fig. 6a); the apparatus, wherein the second code is a correction code (fig. 6a); the apparatus wherein the third code is a gain code (page 1729, section C); the apparatus, wherein the first code represents discrete amplitude value of a peak envelope for the input signal (page 1729, section C); the apparatus, wherein the tracking filter is configured to extract, in response to converting the bitstream into the first code, information from the bitstream indicating whether the input signal exceeds or falls below the reference signal (page 1729, section C). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Hormati’s apparatus with that of Fu Kuan et al. for the purpose of improve the apparatus.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 – 16, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hormati (US Patent Number 11,303,484) in view of Konstantinos et al. (USPGPUB 2010, 0120386).
Regarding claims 13 – 16, 18, 19, Hormati discloses all the limitations of the claims except the apparatus wherein the sampler circuit comprises: a multiplexer configured to output, as the input signal in response to selecting between a non-inverted signal and an inverted signal, the non-inverted signal or the inverted signal (claims 13, 18, 19); the apparatus, wherein the non-inverted signal and the inverted signal are a differential output pair of signals (claim 14); the apparatus wherein the non-inverted signal is 180 degrees out of phase with the inverted signal (claim 15); the apparatus, wherein the multiplexer is configured to alternate, in response to a transition of a comparator clock, between the non-inverted and inverted signals. However, Konstantinos et al. apparatus wherein the sampler circuit comprises: a multiplexer configured to output, as the input signal in response to selecting between a non-inverted signal and an inverted signal, the non-inverted signal or the inverted signal (paragraph 0065); the apparatus, wherein the non-inverted signal and the inverted signal are a differential output pair of signals (paragraph 0065); the apparatus wherein the non-inverted signal is 180 degrees out of phase with the inverted signal (paragraph 0065); the apparatus wherein the multiplexer is configured to alternate, in response to a transition of a comparator clock, between the non-inverted and inverted signals (paragraph 0065). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Hormati’s apparatus with that of Konstantinos et al. to improve the performance of the invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
